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The original schematic shows two cascaded CMOS inverters. The outputs are taken from the common-drain node. In your schematic, the drain is tied to ground and the output is taken from the common-source node. As Elliot has detailed in his answer, your buffer gate will not work. A two-transistor buffer is nothing different than a push-pull (a.k.a. totem pole) ...


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No, your proposed buffer will not work well. MOSFETs are not ideal switches. For example, to make an NMOS conduct well you must bring its gate voltage significantly above the source voltage. In other words, when the transistor is conducting the source voltage must be significantly less than the gate voltage. In your buffer, if you bring the NMOS gate to Vdd ...


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Yes, this design is not power efficient. One lower-power alternative that is widely available is the CMOS NOT gate: In this design, we eliminated power consumption by R2 and the BJT's base-emitter junction, because a MOSFET has 0 gate current at steady state. And we eliminated power consumption by R1 by replacing it with a p-channel MOSFET that will be in a ...


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Maxim has an app note on this subject that seems a bit overkill but here ya go: https://www.maximintegrated.com/en/design/technical-documents/app-notes/4/4624.html


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Here's a circuit using a ratchet relay.


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The minimum supply voltage of HC family logic devices is specfied as 2 V. If you use the search function of any logic manufacturer or distributor, you will find that logic families with supply voltages as low as 0.8 V exist (e.g., AUP, AUC). Alternatively, use a comparator, where you can set the reference voltage directly.


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a CMOS part like CD4011 ot 74HCT00 is a good choice, they are reasonably energy efficient which important if you're running several hundered chips. maximum clock speed won't be spectacular, but should be enough to run demosnstation programs. if you assemble the CPU in parts and test each part you should eventually have a working machine.


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Here's the logic. And here's the timing diagram. Relay 'A' would set and reset on alternate pulses of the reed switch.


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That may have been true at some point, or it may not have been a CMOS output. CMOS outputs typically use symmetrical output strength, but it means that the weaker PMOS transistor can be made larger than the stronger NMOS transistor to compensate the strength. LS TTL outputs do have asymmetrical drive strength, but LS TTL inputs also have asymmetrical input ...


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I used 74LS logic gates on several projects before 74HC(T) came along. The 74LS outputs were damaged easily by accidental shorts or overloads. Such shorts came about through careless use of 'scope/DMM probes, bad wiring in wire-wrapped boards or lash-ups and so on. I saw ICs with visible heat damage or even sections of package cracked off by it. In ...


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Boolean algebra is an abstraction. Mathematician Claude Shannon published in 1937 a mathematically sound presentation how relay circuits could be described with Boolean algebra and how a circuit could be constructed if its function is at first described with Boolean algebra. I guess someone before him has noticed the same, but Shannon's writing was a solid ...


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I’ve been learning about Boolean algebra and I’m curious as to why 0 AND 1 is 0. Figure 1. A CMOS AND gate. Image source: All About Circuits. You can see here that the input transistors are field-effect transistors (FETs). The gates are insulated from the drain and source as indicated by their symbols so current from the input doesn't conduct through to the ...


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It depends on what technology the AND gate is built with. The transistors are used as switches. CMOS technology uses MOSFET transistors which use voltage as the switch control, but other technologies can use current, such as LSTTL with BJT transistors. If the AND gate is made with BJT transistors, it will have two transistors in series, and both must be on ...


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I think you have found the simplest way to do it in discrete logic. You could perhaps use a 4 input XOR to combine your inputs and then use a single flank detector, but this could fail if two buttons are activated at exactly the same time. You could perhaps use a 5 channel mux and find a way to use the spare channel as the flip-flop As you only need your ...


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Two TPDT electromagnetic relays would suffice. Here's the schematic.


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I'll give a verilog version for your reference. Step 1: Assign a different binary value to each state that is currently named in human language. parameter WAIT = 3'h0; parameter START = 3'h1; ... Step 2: The DFF entity holding the current state. (I assume the default state is WAIT here) reg [2:0] st, st_nxt; always@(posedge clk or negedge rstn)begin if(~...


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You can either do it the traditional way with pen, ink, state tables, the TTL Data Book, or simply write it directly in VHDL or Verilog, following the partial example below. Which approach is best depends on circumstances. If this is homework, you probably have to do the former. If you're being paid to get things done, and you don't do the latter, start ...


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One quick-and-dirty test for some kinds of blown TTL ICs is to simply try powering them from a suitably current-limited power supply. If you've "let the smoke out", the blown ICs often appear as open circuits or shorts to the supply voltage.


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It's an AND gate. Give it two inputs from somewhere like buttons and observe output with something like LED or oscilloscope or multimeter.


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If it were to be implemented using NOR gates only, eight is the minimum number while it is just three in case of NAND gates.


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