New answers tagged

0

is correct as written. "If you break/unbreak the over-bar, you change the sign". If you mentally assign a variable (call it u) for "a+b+c", then you are equating ~(u+d) with (~u)&(~d) which is correct and is clearly breaking-the-overbar-while-changing-the-sign. So 1) is good. is also correct, although you took a strange detour. ...


2

Your circuits are better described as logic indicators rather than gates, since their output is light from an LED rather than a logic level. In this spirit here is an 'XNOR' indicator:- simulate this circuit – Schematic created using CircuitLab R3 and R4 produce a fixed reference of 2.5 V. When the two inputs are different the junction of R1 and R2 is ...


-1

Reversing the LED polarity makes your circuit XNOR.. The logic in this and other cases depends on output 1 being indicated by a LED lighting regardless of the actual polarity. This is interesting as learning exercise and can have some application if single gates are useful. Major limits to extended usefulness are. the output in some çases must be floating ...


2

The input would read high if not for the resistors. If you put the switches to GND rather than Vcc the circuit would work (with the switch logic reversed, obviously), however it's not ideal because the open inputs will be a bit sensitive to EMI. It would be fine on a breadboard demonstration with switches. The internal circuit of the 7402 (from the datasheet)...


6

Those are called pull-down resistors. They make sure the signals are 0V when the switches are open. Without the pull-down resistors, the inputs are floating, meaning that you have no control over their voltage. They can be pretty much whatever, and in practice their voltage will vary with the circumstances. Some RF disturbance or you touching the circuit or ...


0

A D flip-flop sets its output \$Q\$ equal to its input \$D\$ on a clock edge. \$\overline{Q}\$ is the logical negation of \$Q\$. So essentially this is an one-bit counter- \$\overline{Q}\$ switches between 0 and 1 on every clock cycle.


0

First of all, you have wrong labels of CLK and E: The first one has E (enable), not CLK. The output is dependent on level - Q copies D anytime when E is high. The second one has CLK, not E. The output is dependent only on rising edge - Q copies D only when CLK is giong LO -> HI. When CLK is HI (or LO) and D is changed, it is not copied to Q. This circuit ...


2

The 74LS33 datasheet specifications do not include a minimum value for the input pull-up current, and the maximum for the output high-Z leakage is quite high: Possibly your inputs will each pull up with 0.4 mA, giving 0.8 mA total which is safely above the output high-Z leakage of less than 0.25 mA. But it is entirely within datasheet specifications to have ...


6

The open-collector output cannot drive the inputs high because the output does not produce a drive current. So you need a pull-up resistor. The value depends on your switching frequency but 10K should be suitable. Typically, logic gate inputs will float high due to input leakage current flowing out of the inputs. With an LS chip, this is a strong current ...


6

It'll work without a pull-up, but it will be slow(er) than normal logic for the 0..1 transition, and it will be more sensitive to noise pickup -- it might have spurious transitions if there are nearby noisy signal lines.


5

TTL went thru about 6 types of circuit design including the classic combinations of std (54/74) , low-power (54/74L) and Schottky (54/74LS,S). In every case the designs follow the same input rules for voltage threshold which is about 2 diode drops = 1.4V. Due to asymmetric impedance the margins for safe design were established from crosstalk as (0.8V to 2....


0

Since the output part has been considered so far, I will make some assumptions about the input part that implements the logic function AND (NAND). Basic logic idea As a rule, basic logic functions OR and AND are implemented by connecting electrically-controlled switches in parallel and series. These techniques are widely used in MOS and CMOS logic gates... ...


10

For the 2-transistor layout, R1 will always be a tradeoff between minimizing shootthrough current through Q1 and Q2 for a LO output (high R1 value) on the one hand and low output impedance on the other hand (low R1 value). In the 4-transistor layout, either T3 or T4 will be on (push-pull layout), so the output pair wastes no current. As a result RC3 can be ...


1

You have master-slave JK FFs showing. To start, here's the transition table for that JK FF: $$\begin{array}{c|c} \text{Transition} & \text{JK FF} \\\hline {\begin{smallmatrix}\begin{array}{c} \text{start }\to\text{ end}\\\\ 0 \quad \to \quad 0\\ 1 \quad \to \quad 1\\ 0 \quad \to \quad 1\\ 1 \quad \to \quad 0 \end{array}\end{smallmatrix}} & {...


0

If output = 1001 (9) then reset ., Then the LSB race from 1000 to 1001 to 0000 might be not noticeable, depending on delays. There may be ways to eliminate the race. (I forget, that was 50 yrs ago). But close enuf for now. You may find they changed methods of counters as each family evolved from 74xx to 74LSxx to 74HCxx for this race condition. But it is ...


11

You can add buffers, but in a good (i.e. robust) logic design you should not need them because you should not be depending on the difference in delays between the different inputs of your NAND gate. Note that there is no guarantee that the delays of the buffers you use match the NAND's delays. If you have a synchronous logic design, then as long as the total ...


4

You had \$ (w+y)(wz+wz')w y + y \$. Let's group it like \$ [(w+y)(wz+wz')w] y + y \$ and look at the subexpression in the brackets. If this is boolean algebra, then whatever the values of \$ w, y, z \$ are, the subexpression \$ (w+y)(wz+wz')w \$ must be either true (1) or false (0). Not 123, undefined, a cat, or anything else. It can't turn into something ...


3

You don't need to learn so many "laws". Initial expression $$(w+y) \cdot (w \cdot z+w \cdot \overline{z}) \cdot w \cdot y + y$$ First, apply identity for AND $$(w+y) \cdot (w \cdot z+w \cdot \overline{z}) \cdot w \cdot y + 1 \cdot y$$ Now, grouping (anti-distributivity) $$\left[ (w+y) \cdot (w \cdot z+w \cdot \overline{z}) \cdot w + 1 \right] \cdot ...


3

Depending on the level of rigour / appeal to axioms expected of you, your professor may be expecting you to state that logical AND and logical OR are both commutative, so that \$A+AB = BA+A\$, but regardless, you're correct. Let \$A = y\$, \$B = (w+y)(wz+w\overline{z})w\$, then the expression reduces to \$BA+A\$, which equals \$A+AB\$, which equals \$A\$ by ...


3

Slightly shorter than Syed's proof is this (W +Y) (W Z + W Z') (W Y) + Y (W + Y) (W (Z + Z')) (W Y) + Y (W + Y) (W (1)) (W Y) + Y (W + Y) W (W Y) + Y W (W Y) + Y (W Y) + Y Y


13

I like the OP's insight better but here is a step by step solution. (W +Y)(W Z + W Z')(W Y) + Y (W + Y) {W (Z + Z')} (W Y) + Y (W + Y) {W (1)}( W Y) + Y (W + Y) (W) (W Y) + Y (W) (W + Y) (W Y) + Y (W W + W Y)(W Y) + Y (W + W Y) (W Y ) + Y {W(1 + Y)} (W Y) + Y {W (1)}(W Y)+ Y W (W Y) + Y W W Y + Y W Y + Y Y (W + 1) Y (1) Y


5

You are correct (although it's not 'basic algebra'). You can prove it by exhaustively evaluating for all 8 combinations of W,Y, Z.


1

As you know, an OR gate outputs "true" if its inputs are not both false. Hmmm... did I just say "not both"? That sounds like a NAND gate to me! So what we can do is have a NAND gate somewhere in the circuit that's connected like this: Input 1: A is false Input 2: B is false Output: A and B are not both false First of all, that output ...


2

If you want intuitive- think of the NAND gate- if either input goes low then the output goes high. So if we invert the inputs (using inverters or NAND gates connected to invert) we have an OR gate.


0

Yes, it is all about applying DeMorgan's law. Basically you can swap OR/AND function by inverting the output and inverting all of its inputs. DeMorgan's law is about how the Boolean AND and OR functions are analogous. Consider this truth table: a b ~a ~b a OR b ~a AND ~b a AND b ~a OR ~b 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 0 1 0 1 0 ...


1

What I would do is use something called LogicFriday. By drawing out the circuit, the associated truth table can be generated to show all the combinations that meet the needed criteria So there are 4 combinations which produce 0b111 output Unfortunately the site did not renew the domain, but can still be found here: https://web.archive.org/web/...


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