New answers tagged

1

For small multiplexers it doesn't matter. Large ones, a gate-implemented mux will take more area and have longer delay. So these use a different structure. More about than in a moment. 3-state buffers don't work well on ICs as this approach can leave the output line floating. This can be overcome with a 'weak keeper' on the line, but there's another way. ...


1

In ASIC design (and probably FPGA design as well), internal logic tri-state gates are to be avoided unless absolutely necessary. There are several reasons why that is the case, but the short version is that the rule keeps you from shooting yourself in the foot, and isn't really costing you area. Note that within a gate boundary, it's fine as long as the ...


0

A line going to the input of a digital logic gate should always be in a known state, either high or low. The alternative is "floating", which means it could be anything at all and is not being driven. In which case, you have an antenna and unpredictability attached to your input. Fortunately quite a few such chips have a high value resistor ...


4

If this is a break before make switch, in the very short period while the switch is changing from one side to the other the input will be floating and can rapidly change state several times. In some instances this would be undesirable. As pointed out in the comments below, even with a non-floating input, switch bounce can still occur. Depending on the type ...


1

Great Question. As others have stated, the first topology consumes constant power when the output of the inverter is low (logic "0"). Allow me to expand upon this with the MOSFET equivalent. As shown below, the resistor-transistor logic (RTL) inverter has a very similar topology, except for the absence of a resistor on the base (gate in this case, ...


1

Forget the idea that 0 is a low voltage and 1 is high. It's sometimes true but not always. 0 and 1 are abstract concepts that do not exist in the real (electrical) world. True and False would be better terms because it'd be less easy to confuse with voltages. The important thing is that digital circuits actively force their output to either True or False, ...


3

The short answer is that you are not comparing apples to apples. Your google image of a single-transistor inverter is not a NOT gate. A bipolar logic (TTL, ECL, LSTTL, Shottkey, whatever) inverter (NOT gate) is much more complex than something left over from the RTL days. To be fair, you could translate the approach used in a CMOS inverter to bipolar ...


4

Several reasons: Firstly, it's counter-intuitive to someone used to designing with discrete components, but in IC design transistors are cheap and everything else is expensive. In the days when pull-ups were used in IC design they were frequently done with weak transistors instead of resistors. Secondly CMOS has the huge advantage of very low power ...


2

Philosophy There is a lot of philosophy in this matter... and it can be revealed through generalized rather than specific explanations because the problem is purely electrical. Specific electronic implementations can only serve as examples that illustrate the general idea. Implementation Input circuit Logic gates, like most electronic circuits, are voltage ...


5

I would add that it is possible to design a digital device that can detect an open input vs. high input vs. low input, thus having a three-state input. This is done by alternately connecting the input to relatively high-resistance pull-up and pull-down resistors. This does result in fairly low sampling rates as the device must let the input settle after ...


4

Zero’s and one’s (low & high) are digital defined by analog values with a margin in between for transitions and noise. No output is floating or called tri-state used on bidirectional busses. However CMOS must never be designed with no input for many reasons and must be terminated low or high as required. No input on TTL is hi, but for noise reasons ...


12

Usually a Logic Low is a low voltage, normally near Ground/Zero volts, and a Logic High is a higher voltage near the positive supply voltage. There is a range of voltages between Low and High where the input state is undefined - we don't know whether the circuit will consider it as a High or Low. If the input of a logic gate is not connected, that ...


7

is Low and High used as an indication of lower input voltage and higher input voltage ? Yes, but some logic families also have current requirements. With TTL, for instance, a logic 0 is not only a low voltage but the driving stage must be able to sink 1.6 mA of current from the input. And if Zero used as a low input voltage then isn't no input can also be ...


20

Your circuit with the bjt is RTL (resistor transistor logic). There’s DTL, TTL, ECL, PMOS, NMOS and CMOS. There’s others as well, but you can research these if you’re interested. Basically there’s a number of different ways to implement digital logic. Each has their advantages and disadvantages. CMOS tends to be the favourite these days due to its low power.


23

It's possible to build this circuit with 2 BJT's or one MOSFET You're reading too much into it. The difference isn't the technology of the transistor, it's method of circuit operation In the first circuit, you can STRONGLY SINK current (drive a very strong logic "0"), but you can't strongly SOURCE current (your logic "1" has to pass ...


31

However, I've always been perplexed as to why people do not use the former method for chip manufacturing. In chip design, resistors take up more area than transistors, and area is one of the main drivers of chip cost. In the BJT design, when the output is low, there is a current running continuously through the resistor. This consumes power and produces ...


1

I'm not sure of the exact implementation as a circuit but it may be helpful to write your function this way: $$ \begin{align} A(v) &= v^{v/a} \\ \ln A(v) &= \frac{v}{a}\ln v \\ A(v) &= \exp \left( \frac{v}{a} \ln v \right) \end{align} $$ Here \$a\$ is a constant, like 4 mV in your example. This last formula can be computed using analog ...


1

This is the basic structure: simulate this circuit – Schematic created using CircuitLab The basic principle is to exploit the exponential nature of the diode response.


1

You are correct, that the overvoltage figure basically does not matter as long as the current is bounded to safe limits. All the absolute maximum ratings I have seen still mention the voltage limit. Guess it cannot hurt to avoid at least a few dumb user mistakes. Pulling up the output to 12 V via 10k sounds tolerable. 1 mA is far below the maximum rating. ...


1

IThe equivalent circuit for the noise source by itself is found by zeroing out all of the other voltage sources (principle of superposition). Consider how RC2 and Q4 are connected. The collector of Q2 can be ignored because its effective impedance is much larger than RC2. The effective resistance of this combination (hib4) is RC2 divided by the current gain (...


5

\$'\$ is complement operator in that context. \$A'\$ is also equivalent to \$\overline A\$. It signifies a negation on boolean variable \$A\$, ie., \$\text{not } A\$. So the expression in your question will become:- $$C=(\text{not }A) \text { and } B$$


1

I'm having similar problems with other config and just to point out, if you read the Phillips datasheet, which by the way is wonderful reading, the 74HC has some more variations which are dependent on the Vcc input. HCT are more stable and have fewer variations, also they have some internal plus: The 74HCT input stage is similar to that of a 74HC device. It ...


0

This should do it. First clock pulse in clocks a high through to Q output of first flipflop and lights first LED. Second clock pulse in clocks high through to Q output of second flipflop and lights second LED (first LED stays lit). Pressing SW1 resets both flipflops and turns both LEDs off at end of game. C1 in conjunction with R4 is a power-on-reset ...


0

The circuit you drew is purely combinational. It assumes that one of the top three inputs is asserted, and one of the bottom three. This is fine for learning basic combinational logic, but it's not what you'd really want to do for this. Fine for now. What you're really asking to do though is to track the history of winners. There's nothing special about ...


1

Yea, assuming zero wire delays, the correct answer is 28 ns. It is the critical path aka worst-delay path to the output, which is relevant to the timing analysis of the circuit: \$ A/B \rightarrow AND \rightarrow AND \rightarrow OR \rightarrow F2 \$


2

In CMOS (as in most logic families) we always want to avoid shorting the power supply to ground. So, let's say you have a NAND gate that looks like this: We need to make sure that if the path from Z to ground is on then the path from Z to Vdd must be off. So, in order for there to be a path from Z to ground, both N1 and N2 must be ON. For that to happen, ...


4

Complementary does not mean there is an inverter circuit. Complementary means, there are both NMOS and PMOS transistors, as logic that existed before CMOS had only NMOS transistors. In a CMOS circuit, NMOS transistors are able to pull strongly low, and PMOS transistors are able to pull strongly high.


1

The "complementary" in CMOS refers to the field-effect transistor fabrication process that uses complementary and symmetrical pairs of p-type and n-type MOSFETs for logic functions. (This is instead of all p-type or all n-type transistors.) If you can post a schematic of your series and parallel circuits we can address those too.


9

The hardware equivalent of an if/else is a multiplexer. if select_input == 0 output = input_0 else output = input_1


1

It sounds like a multiplexer to me. Hover over the multiplexer tag below your question for an SE definition. TutorialsPoint has some good explanations of both: A Multiplexer is a combinational circuit that has maximum of 2n data inputs, ‘n’ selection lines and single output line. One of these data inputs will be connected to the output based on the values ...


0

Okay, I think I'm seeing it. So when the filament is cold, there's a 20:200 ratio in the voltage divider and about 11.5V at point A. I drop about 0.7 over the BE junction and the rest goes across Rb. If I size Rb at 2.4M I get about 5uA. With the beta of 200, I should get about 1mA through Rc. No. That is called dangle-biasing, and is extremely unreliable. ...


3

I suggest you use any Nch FET to act as a constant current source as long as RdsOn <=1 ohm or so and not use an NTC thermistor. Inrush current limiters (NTC’s) are not intend to be run continuously as they transition at high temperatures which reduces lifespan. I can use a simple 5mm RED AlGaAs LED as a Zener of 1.9V @ ~5mA to bias the NPN current limit ...


0

Thanks to all those who have commented, I see the Rb is definitely required. When the circuit is cold, the filament to inrush limiter voltage divider ratio is 20:200. With a 12.6V supply, the voltage at point A is about 11.5V. 0.7V is dropped across the base-emitter junction. This leaves 10.8V across Rb. If I'm trying to get 1mA of collector current with a ...


0

GAL16V8 ; this is the second example Exa.2 A B C D E F G NC NC GND NC NC NC NC NC NC Y3 Y2 Y1 VCC ... Y3.T = /G Y3.E = E * F DESCRIPTION tristate output: pinname.T tristate control: pinname.E -- https://github.com/daveho/GALasm/blob/master/examples/Tristate.pld from the documentation for GALasm, which seems to be a popular ( ...


3

When you said "feed its output to its own input" I thought you meant: This would not work with an OR gate as it would forever output "1". Also the power-up state is undefined. Besides that, your circuit will work fine, except propagation delays will not be matched so when several inputs change at the same time, the output may glitch ...


3

Yes that is possible, but take the propagation delays into account. These will stack for every stage you wire in series. Therefore, propagation delays from different inputs to the output will be slightly different. In your example 1,2,4,5 will have thrice the stated prop. delay, whereas input 9 will have only twice the stated prop. delay.


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