New answers tagged logic-gates
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Boolean circuit - 4 inputs (A, B, C, D), and output Z performs the function: Z =1 for all numbers divisible by 3
(1) Numbers divisable by 3
As you have four input bits, you can represent the numbers 0-15.
Therefore, Z=1 for (A-D)=3,6,9,12,15
...
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Boolean circuit - 4 inputs (A, B, C, D), and output Z performs the function: Z =1 for all numbers divisible by 3
1 = 1 (mod 3)
2 = -1 (mod 3)
4 = 1 (mod 3)
8 = -1 (mod 3)
You're looking for numbers that are equal to 0 (mod 3), which means they have an equal number of "1" and "-1" bits set. ...
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How do I implement a bit adder?
As your question does not state a clear application like:
Discrete Logic
HDL
Software (C e.g.)
i am covering all three:
(1) Software
...
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How do I create a 8-bit binary digit out of the combination two 7-bit ASCII values?
One solution would be an off-the-shelf ROM chip. But it does require you to obtain a suitable ROM programmer.
If you are certain that the inputs are always valid ASCII digits, then you only need the ...
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How to split an n-bit pin into n 1-bit wires [in Logisim]
The Splitter component in the wiring folder can accomplish this
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How do I implement a combinational circuit that finds which input has more ones?
Do you want a really easy ways to do that?
Include some analog circuits.
Buffer both inputs with buffer gates, all powered from the same 5 V supply (this is to ensure that the voltage from each high ...
- 13.7k
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How do I implement a combinational circuit that finds which input has more ones?
Start with the simplest thing that could possibly work (XP).
It is OK to select A if
• A = B
• A = 1111111111111111
• B = 0
• A contains at most one 0s (an or of 16 15-input ands) and B != ...
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Solar panel as light sensor to switch a battery and LED circuit
This worked well for me to simply use a solar module as the "dark detector". Here is an explanation.
The first image shows the circuit and the parts used. The second image shows what I ...
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Tie an input of an AND gate to its output
The wealth of SE EE
I have always said that the biggest asset of SE EE is not the answerers, but the questioners because what we explain can be found in sources but such original, interesting and ...
- 12.8k
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Tie an input of an AND gate to its output
The result is influenced by the analog nature of the otherwise binary device.
The output is one of the inputs. So there will always be two inputs. During the day power-on transient the gate will act ...
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7
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Accepted
Tie an input of an AND gate to its output
Depends on the initial state of the output!
Output is LOW at t0
Now your input signals are LOW and X... AND requires two HIGHs....So the Output will remain LOW independent of any change on X
Output is ...
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How is a CAN bus like an AND gate?
An AND gate logic table would be like this:
AND gate (x and y are input pins)
x y out
0 0 0
0 1 0
1 0 0
1 1 1
Now if we instead say that x and y are two ...
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How is a CAN bus like an AND gate?
The signals on a CAN bus are similar to those of the i2c: essentially, a "wired AND".
There are different nodes which when idle (or when writing "1"), leave the line floating (...
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How is a CAN bus like an AND gate?
I'll try to explain using this simplified structure below:
simulate this circuit – Schematic created using CircuitLab
Note that the CAN Bus physical layer is not actually like shown above but ...
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9
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How is a CAN bus like an AND gate?
When you map the CAN bus state into a truth table, you get following:
This is the same logic you'd get for a n-channel AND gate.
As the term suggests, a dominant bit will always overrule a recessive ...
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Is there any tool that can create a logic circuit equivalent to some Verilog code?
Digital Logic Simulators—
DigitalJS Online - http://digitaljs.tilk.eu/ Verilog to Circuit
Visualizing Verilog Simulation | Hackaday
FPGA | Hackaday
A Breadboard In A Browser | Hackaday
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Accepted
Have I made this XNOR gate right?
If your circuit works then it works. However, it's a bad idea to share the same resistor with the base of multiple transistors, because they could use different voltages to turn on (due to ...
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How do you separate a logic gate from the circuit implementing that logic gate?
I think the reason this feels nonsensical is that your input and output are different types of logic signals. The input is 5V when high and 0V when low and current goes into the input. The output is ...
- 11.6k
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What is the purpose of chaining series of NOT gates?
It’s a fixed delay if the supply voltage is constant. It can also be a voltage controlled delay if the supply voltage is adjustable. That works quite well in the CD4000 family where then 3V to 12V ...
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What is the purpose of chaining series of NOT gates?
Another benefit of chaining NOT gates is to ensure a maximally fast rise time in the output signal when the input signal has a slow rise time. This usually only requires two or three NOT gates.
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What is the purpose of chaining series of NOT gates?
As other answers pointed out an inverter chain or buffer is introduced to produce some delay. In digital integrated circuit design, adding buffers is one possible solution to fix hold time violations. ...
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