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when in reverse active mode, and 2 emitter are in logic high, how is the collector current calculated ? Both emitters are reverse biased and Q1’s collector current is wholly sourced via the base resistor with the base-collector region acting as a forward biased diode.


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Parallel PROM and RAM chips are the simplest form of programmable logic. When most people think about these chips, they simply see it as a medium for data storage, not too different from a hard drive. When software programmers think about them, sometimes they visualize it as a table lookup or array indexing process: one sends a n-bit address to the chip, ...


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If you are looking for an off the shelf part having two inputs and one output, a multiplexer can be used to do the job. Inputs on control lines and MUX inputs connect to the appropriate logic levels to produce the functionality needed.


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Any PLD, CPLD, or FPGA (three generations of programmable logic chips) has a programmable gate array that can emulate a wide range of logic functions. In terms of a non-programmable, off-the-shelf chip, the closest thing probably is an AND-OR-Invert gate. https://en.wikipedia.org/wiki/AND-OR-Invert


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Your original question was confusing. I have edited your question, hopefully to make it clear. So what you are building is a transistor inverting switch, and you want to turn the LED (D2) on and off by shorting it via the transistor, and the transistor is controlled by an output pin of an Arduino or Raspberry Pi. There are several potential problems, Make ...


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The first expression has one, 3-input OR gate. The second has two, 2-input OR gates. These two expressions are logically equivalent. Whether either one is simpler than the other depends on your definition of simple. Does simple mean fewer gates or does simple mean that you only use 2-input gates? In the real world, optimization is usually done to minimize ...


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There are 2 paths for X and 3 paths for Y to F. You can see it both in schematic and functional equation. \$F= (X!+Y!)\cdot ((X+Y!)\cdot Y)~~~\$ or \$F=(X!+Y!)\cdot (X\cdot Y+Y\cdot Y!))\$ If input = LH we use the inverted delay tHL for the inverter output and same polarity for OR,AND. Thus the metastable transition times may be added up as follows. ...


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The first thing to do is draw a truth table. This will clarify your thinking and is much easier to understand than a list of bullet points. Table 1. The required functionality. 'X' is don't care. Timer Above low Above high Humidity On temp SP temp SP high Out -------+---------+----------+----------++----- 1 | 1 | 1 | X ...


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Time is 0 and Humidity must be 1 but there is no logic gate that supports this. Am I wrong? You're generally not going to find many IC's offering specifically an AND gate with one input inverted. But there's no reason you can't make one by combining gates from two different IC's, by using a (C)PLD or by using MCU software. Additionally, NAND and NOR are ...


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"My problem is when the robot meets an obstacle it just reduces the light intensity of LED". This suggests your logic gate works as you intended. Judging LED current by eye, versus judging current threshold with the opamp suggests the fault lies with the opamp. Using an opamp to detect an obstacle-in-path is not a good idea. This is a job for a comparator. ...


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I've drawn your original receiver stage on the left, and an improved one on the right. A photodiode generates current proportional to the light impinging on it, plus a bit of leakage current (called "dark current" in the datasheet). A transistor will pretty much amplify any base current -- so the circuit on the left will always have some collector current, ...


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The PMOS turn on when the voltage is low. So you have a pull up network with two parallel legs. The first leg has two transistors in series, which means that both need to turn on for the output to be pulled high. This is your \$\bar{A}\bar{B}\$ term. The second leg has a single transistor. This is your \$\bar{C}\$ term. Because they are in parallel the pull ...


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The AND gate's inputs are wired together, so it is acting as a simple pass-through buffer. This will probably be there because the source of the signal does not have a low enough output impedance to drive the RC filters that follow. Furthermore, it may also act as a level-translator for the input signal.


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We can only guess, but it is most likely a buffer, both to speed it up and to reference it to the 3.3V supply going into L1. If I were implementing something like that, I'd make sure that the 3.3V supply was exceptionally clean, possibly even regulated from some higher voltage for no other purpose than to provide power for that AND gate. The reason for ...


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