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What's happening is that when you have R1 set to zero, and 50 ohm impedance on the supplies, the 3.3V and 12V supplies are forming a voltage divider (they're modeled with a series resistance, as you set.)
So you're getting the voltage midway between them plus the diode drop Vf, so:
Vout = (12+3.3)/2 + 0.3 Vf = 7.95V.
To visualize this better, set the ...
2
A quick way of adjusting the zener voltage of a spice model, is by creating an alias to it and modifying the properties you need, e.g.:
The zener diode D1 uses a model called MYD, which is nothing but a copy of the built-in zener diode BZX84B8V2L but with a different zener voltage (5V in this case).
You can also create a model from scratch using the ...
2
To turn off that FET, the gate driver Vout needs to be up at 24 volts.
This circuit does not provide that.
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Can you help me to solve this problem?
I can't be absolutely sure but, you appear to have got the 2 pins labelled FB and SW swapped AND you omitted the all important flyback diode: -
I'm not saying that your LM2842 spice model (internally) hasn't got problems but, I am saying that what you have drawn is sooooo wroooooong! Fix it then try again.
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You can use this command:
.meas tmp find V(o) when abs(v(o)-1)=0.01 fall=last
Alternatively, you can concoct something like this for a more "dynamical" approach:
I commented out the .step card so that the results are a bit more visible. This is just one approach. Note that this implies knowing the I/O step value(s). I suppose you can do that by simple ...
2
Your circuit is flawed. The diode is ineffective. The pulse waveform that drives current into the transformer primary is returning to 0 volts and hence the primary current remains approximately where it got to when the pulse was ramping up the current. This is because: -
$$V = L\dfrac{di}{dt}$$
Hence, if the voltage is zero, then the rate of change of ...
2
Try this: for all sources add Rser=0.1, and for the 3V one add Cpar=1m, and for both capacitors add Rser=10m. If (unwanted) very high frequency oscillations start to appear because of the inductor, try adding Rpar=100k to the inductor, or even lower. Don't shy away from setting parasitics, they helo with convergence. If need arises, also don't be afraid to ...
1
When a simulation descends to machine limit calculation it is a sign that the simulation sees or expects chaotic output.
This can be due to a divergent solution (e..g runaway positive feedback, multiple voltage dependent sources ) without same limits on power or frequency or otherwise .
If you are really testing 1600 transistor models and some exhibit this ...
1
This is a little crude, but I think it does what you are asking (sorry for the screen grab but links from the schematic editor are not working for me right now)
R2 and R3 bias Q1 so it turns on when the emitter is near 0V. They're not optimized and the turn-on will vary with temperature.
If you want something much more precise, consider a comparator ...
1
Solution from ADI Engineer Zone:
https://ez.analog.com/design-tools-and-calculators/f/q-a/163106/ltspice-meas-command-unexpected-single-fail-in-step-when-the-rest-passes-ok
Hello Marcin,
I have seen this kind of problem sometimes. The solution is very
simple. Just compare with a smaller value. Often a factor of 1e.9 will
be sufficient as in your ...
1
http://bordodynov.ltwiki.org/
There are models of photo transistors.
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(polarity should not matter for MOSFET on Drain and Source)
It does matter for MOSFET's. Maybe you're mixing up JFET's?
Vto is the same as VGS(th), so, the voltage between Gate and Source.
The upper circuit/simulation
You shorted gate to source, so VGS = 0 V. The default parameter for Vto is 0V.
Therefore, the mosfet is in cut-off mode and the current ...
1
You need to add this statement:
.model nmos nmos Vto=-1
And then everything will work as expected.
1
If using the wave export function is not possible (with or without attenuation before/amplification afterwards), then you can also export the results of the simulation as ASCII: select the waveform window, File > Export data as text. After that, the newly created file will have the first line identifying which column belongs to which data, e.g. time V(x)....
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What are the FETs, specifically what are their input capacitances?
What is the AD711 output (the gate drive) doing?
If these are high power MOSFETs (and I really don't see why you need 300Vpp when you can't use most of that range : the FETs are source followers so the output can't exceed the AD711 output range) then they have huge input capacitances ...
1
The AD8221 is specified to work with a maximum supply of plus and minus 18 volts. You have applied plus and minus 30 volts. Yes I know it’s a simulator but why should the model be expected to perform sensibly at levels way beyond what the real chip is designed to operate at.
Also, I see that your driver rails might create much bigger voltages than what the ...
1
In LTspice, a commonly forgotten aspect with using inductors is its default series resistance of 1 mΩ.
Make sure to explicitly set it to zero to get even better matching results!
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Maybe the accuracy error lies in the number of simulation points? Using the built-in fft-function in LTspice (.four 1000k 1 -1 V(Vi) V(Vo)), I got large discrepancies in magnitude and phase by running your simulation with standard simulation settings.
By decreasing the maximum time step, I managed to get magnitude and phase shift almost identical to the ...
1
You can use the .meas commands for that. Suppose V(x) is the waveform of interest, and you're interested in time=1m:
.meas tmp param V(x) at 1m
After the simulation is done, activate the schematic window and press Ctrl+L to bring up the error log. Right-click inside it and choose Plot .step'ed .meas data. The newly opened window will have the variation of ...
1
Here in these LTSpice snap shots I modeled the popular MFJ regenerative receiver circuit so that I could add an AGC circuit to the audio later on. I have the tuning coil L1 with an inductance value stated as {lt) and C7 capacitance is stated as {ct) these two components will then be tuned in an AC Anlysis Plot with various component values that the software ...
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