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10

The simple answer is maybe, but probably not. It really depends what is using the memory. It is important to consider the structure of the memory. The M9K memory modules are true dual port. This means that they have two independent read/write ports. Each of these ports has one address bus, one read data bus, and one write data bus. What that means is that ...


7

You'll need to set up Quartus to produce a POF file. You can either generate a POF directly or convert a SOF to a POF. This file can then be loaded into the flash memory. See page 37 of this document: https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/max-10/ug_m10_config.pdf . Once you have generated the POF file, it can be ...


6

Intel provide an Excel spreadsheet that allows you to put in various parameters (e.g. clock speed, resource usage, IO count, PLL usage, etc) which gives an estimate for the current requirements for each of the power rails. You can download it from here. In case the link goes dead, the page title is "PowerPlay Early Power Estimator Download MAX 10 FPGAs ...


3

I've already know that the bank 1 and 8 need to be powered up with the core Under these circumstances FPGA exits power-on-reset and starts configuring, see here page 2-26. But it is a good question if it will function properly in user mode. The question is, for all the other banks, bank 2 to 7, is it safe to power them up and down separately? There were ...


3

It's an FPGA. You can have an UART on as many pins as you like until you run out of logic elements.


2

I think the standard method for doing this is to generate an SVF or XSVF file with the Quartus software and then using something like OpenOCD or http://www.clifford.at/libxsvf/ to play it back. You would interface to the FPGA via the JTAG pins, either via GPIO or perhaps an FTDI chip. Another option would be to forego the FPGA's onboard configuration ...


2

HS up to 1.5Gbps and LP upto 10Mbps HS 340mV into 50Ohms per side using CML current source to get +-340mV LP uses 1.4V driver unipolar reduced to 0, 340mV by impedance divider as a CM signal while not causing HS imbalance of more than =≈5% differential offset. So LP is a common mode voltage driver at <10M speed and HS is CML differential up to 1.5G all ...


2

Suppose the router runs that reference clock input alongside some 2.5 volt FPGA signals that transition in 50 picoSeconds, and the parallel-distance is 1mm and the separation is 1micron. Assume the dielectric constant Er is 5. Let the reference clock be 10MHz with 1nanosecond edges, and also 2.5 volts swing. How much jitter will be created? Or another way ...


2

VHDL and verilog almost precipitated out of thin air around the same time -- the early 1980's -- by completely different actors but for what in hindsight looks like similar reasons. Their purposes were more about documenting digital ASIC and/or logic systems, than much else. It wasn't long before the idea of trying to simulate them came about (a year or two ...


2

Quote from the stratix link: Yes, you can power down the VCCIO voltage of unused I/O banks in Stratix® IV devices. The Stratix IV device Power-On Reset (POR) circuitry does not monitor the VCCIO of the I/O banks, thus you do not need to power up the VCCIO on banks which are not using any I/O pins. Altera® does not characterize device ...


2

To directly answer the question, there is nothing in what a CPLD is to prevent you using VHDL to build circuits for one. CPLDs in essence are basically the same as an FPGA with the exception that they are non-volatile. That is their logic configuration will remain even after powering it off. By contrast FPGAs are volatile (typically SRAM based) and so ...


1

This only applies to "signals when switching the clock source to the PLLs or GCL". So if you want to switch a clock to a PLL then you can do so by disabling one clock and enabling another. The PLL functions like a clock buffer to some extent. However downstream from the PLL the clock should not be ran through logic because it will provide a mismatch of ...


1

The datasheet will be correct. Notice the table states that the unit is "millimeters". I dont know why the Eagle dimensions are wrong. There doesn't seem to be any dimensional data in the BSD file, so I'm not sure how Eagle can interpret it. In fact, in the BSD file it says at the top: Package : 8 mm 153 MBGA Which matches the 8mm of the datasheet.


1

@Sid, the referenced PMOD PCB is a level translator. It will convert the CMOS (3v3) voltage levels on the Altera MAX-10 to RS232 compliant voltage levels. Respectively, your PC interface must be also of RS232 levels (NOT 3v3 voltage swings!!) to interface with this PMOD. Having said this, your MAX 10 or whatever FPGA you wish to use must offer 2 GPIO pins ...


1

I hope you solved your trouble at this time. From what I learned from MAX10: JTAGEN has no influence on programming, on all my board it is now pulled down (I use 10k), this prevent entering JTAG when I/O sharing is selected, no influence if JTAG sharing inactive. NConfig, Nstatus, Config_Done need a pullup, never use these pin as input, low on power up ...


1

Some updates. If it helps anyone: "Timing requirements not met (inst5|altpll_component|auto_generated|pll1|clk[0] setup slack: -2.197, endpoint tns: -8.124) on the PLL output." This warning occurred because I was using in the design both the 8mhz PLL clock input and the generated 80mhz PLL output. Possibly generating meta-stable conditions. Solution was to ...


1

Boundary scan (and internal scan) testing, whether using JTAG or not are intended for production test. This is completely different to using JTAG or SWD for software debug. Sometimes the same pins will be used, but this is not a given. It looks like the Altera USER0, USER1 instructions are used to access internal (user connected) scan chains. This permits ...


1

With an un-terminated line that is long enough and driven fast enough, there is a potential for overshoots with voltage level high enough to exceed the rating of a MAX10 input. There is a "PCI clamp diode" for each MAX10 I/O pin that can clamp the voltage. The clamp diode is connected between the pin and Vccio (AN447 figure 2). Therefore the voltage is ...


1

See this table from the datasheet (sorry its small, click on it for a better view). The table is the same for LVTTL with the exception of \$ V_{OH} \$ which would be 2.8V (which is still larger than 2.4V) so it really wouldn't make a difference for almost all applications. For LVCMOS however the current requirements are different between 3.0V and 3.3V. So ...


1

The I/O during configuration are inputs. Refer to the MAX I/O User Guide, page 2-13. I really don't understand your sentence, about you not using a reset. I really don't think it is a good practice not to use reset in a digital design.


1

That part does not support ADC functionally. Page 4 of the device overview specifically states that SC parts are the compact functionality cores which do not feature ADCs. Only the SA and DA parts have analogue features.


1

This is more of a guide how it could be done. EDIT: You need: for first time programming: QuartusII, QSYS, NIOS SBT, JTAG connection to your FPGA and for remote upgrade: a terminal programm which is capable to send files and UART connection to your FPGA. Max10 supports dual-compressed image mode. You can read about its flash memory here. Create a golden ...


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