Hot answers tagged

85

Intel's Haswell (or at least those products that incorporate the Iris Pro 5200 GPU) and IBM's POWER7 and POWER8 all include embedded DRAM, "eDRAM". One important issue that has led eDRAM not to be common until recently is that the DRAM fabrication process is not inherently compatible with logic processes, so that extra steps must be included (which increase ...


49

.text The .text segment contains the actual code, and is programmed into Flash memory for microcontrollers. There may be more than one text segment when there are multiple, non-contiguous blocks of Flash memory; e.g. a start vector and interrupt vectors located at the top of memory, and code starting at 0; or separate sections for a bootstrap and main ...


46

There are several reasons for this. First of all, memory takes up a lot of silicon area. This means that increasing the amount of RAM directly increases the silicon area of the chip and hence the cost. Larger silicon area has a 'double whammy' effect on price: larger chips mean less chips per wafer, especially around the edge, and larger chips means each ...


37

Unless you have an initial state programmed, it will be more or less random. Although this may vary with different SRAM implementations. You also say "blank". Some might think that random is "blanker" than all 0's. SRAM memory stores memory on back to back inverters. This forms a bi-stable system (two very stable states with metastability dividing ...


29

The original electronic nonvolatile memory is based on ferrite cores. While it's relatively easy to magnetize such a core in one direction or the other to store a one or a zero, it takes some fairly sophisticated circuitry to read it back reliably. Modern nonvolatile chips rely on charge storage, but in order to make this work, you need to be able to create ...


29

Personally I use FRAM, it is easy to use and you can get 32K by 8 for a few dollars. It works like the EEPROM modules but there is no delay or limits on reads and writes. These can be purchased on Arduino modules about 3/4" by 1.25" in 3.3 and 5V. Per the Cypres data sheet: "The CY15X102QN is capable of supporting 10^15 read/write cycles, or ...


28

Normal embedded system: Segment Memory Contents .data RAM Explicitly initialized variables with static storage duration .bss RAM Zero-initialized variables with static storage duration .stack RAM Local variables and function call parameters .heap RAM Dynamically allocated variables (usually not used in ...


27

Using dynamic memory allocation on a 16 bit MCU with 4kb RAM is very poor engineering. Not so much because of the usual problems with memory leaks. Not so much because of heap memory fragmentation. Not even because of the rather steep execution time overhead needed for the allocation routines. But because it is completely pointless and makes no sense. You ...


27

It is very simple. Number of pins and cost of packaging. EEPROM devices are primarily used to store parametric data or characterization constants for a device. The typical scenario is to write very seldom and read typically once each time the host device boots up. For this type of application the relatively slow writing times of EEPROM are of little ...


27

I need to be able to update data multiple times a hour so I expect EEPROM to become useless Actually... this is not 100% true. Check your EEPROM datasheet. For a very basic and common EEPROM (for instance I checked the Microchip 24LC256) you have at least 1 million write/erase cycles. If you write ten times an hour 24/7 you will have 10 * 24 * 365 writes a ...


25

In both cases (EEPROM/flash and DRAM) a small (femtofarads) capacitor is used. The difference is the way the capacitor is connected. In the case of DRAM it is connected to the source or drain of a MOSFET. There is a tiny bit of leakage through the transistor channel and the charge will leak off in a relatively short period of time (seconds or minutes at ...


25

Memory addresses are binary numbers. The range of an N-bit (unsigned) binary number is 0 to 2N-1, a total of 2N different values. Since addresses are passed to memory chips as binary numbers, it makes sense to build them in capacities of powers of 2. That way, none of the address space is wasted, and it's easy to combine multiple chips/modules to build ...


24

No, they're not the same type of RAM, even though they're on the same chip that uses the same manufacturing process. Of all the caches, the L1 cache needs to have the fastest possible access time (lowest latency), versus how much capacity it needs to have in order to provide an adequate "hit" rate. Therefore, it is built using larger transistors and wider ...


24

Nowadays, Flash memory is used to hold program code, and EEPROM (Electrically Erasable Read-only Memory) is used to hold persistent data. Back some 30 years ago, before Flash came along, EEPROMs were used to hold program code. Actually ROM (Read-Only Memory) came first, then PROM (Programmable ROM, once only), EPROM (PROM Erasable with UV light), EEPROM, ...


24

Just pick a bigger EEPROM, and write it sequentially. Suppose you have a EEPROM family which withstands 10000 write/erase cycles, and you need 100 times more. Then pick a 1 MB EEPROM form the same family, and every time you need to write, use the next unused 10 KB instead of erasing the whole chip. Only erase once the whole 1 MB is full. You'll end up with ...


22

You cannot extend the program memory (flash). TI produces the same chip with double the flash and RAM, but nothing else changed: TM4C1230D5PMI. If you cannot use a chip with larger flash, you will have to reduce your code size: Disable debugging, such as the expensive printf function. A printf that supports floating point output will typically set you ...


21

I can't speak about FRAM (ferroelectric memory), but any technology that uses floating gates to store charge — any form of EPROM, including EEPROM and Flash — relies on electrons "tunneling" through a very thin insulating silicon oxide barrier to change the amount of charge on the gate. The problem is that the oxide barrier is not perfect —...


21

Three non-volatile memory types match your needs, in order of available size: Wear leveled EEPROM/FLASH. Battery backup SRAM. FRAM. In terms of cost, FRAM is best. All you need is inside the chip, including backup capacitors to complete writing. However available sizes are low. Battery backup SRAM is large and costly in materials. Wear leveled EEPROM ...


21

Here is what I did on a product that's still in mass production. Keep all the parameters and counters in RAM Hook up an interrupt line to a power supply voltage threshold detector When the interrupt triggers, shut off everything that consumes power (most peripherals, LEDs, etc) and back up all the RAM to flash. Turns out there was about 10-20ms of time ...


21

Although they both involve changing the contents of memory, writing and programming are not the same thing. Writing is done with the chip connected to the processor, during a normal processor cycle, and using normal voltages. Programming involves conditions that are not normally produced by a processor. There may be a need to erase the memory first (...


20

Personally for hobby projects I tend to use the most powerful microcontroller in the family with the right footprint. I then develop the PCB, write some code and produce a prototype. This has the advantage that I know the small number of microcontrollers fairly well, so I can rapidly prototype without having to read a whole datasheet. I also have breakout ...


20

Whatever you declare as a variable in your code will be in the RAM of the PIC, and thus will disappear when you power it off. However, the PIC18F2580 has 256 bytes of EEPROM memory, which is non-volatile. You can store your phone numbers there each time they are modified, and load them at boot to your variables. To read and write a byte to a given address ...


20

It literally stores lines of machine code from program memory (aka the entire instruction you line in your original post. The fact you even discuss "storing all possible op codes in cache" points to a deeper misunderstanding. Talking about storing all possible op codes in cache (or any memory for that matter) has no meaning. All the possible opcodes that ...


20

General advice SDUC (ultra capacity, > 2 TB) cards don't support SPI according to the specifications. There are several libraries that significantly simplify accessing the SD card, using a proper file system so that the files can be read easily with a file explorer on the computer. If you can, I would suggest stopping here and giving them a try, because ...


19

The main reasons larger memory (GB's of DRAM) isn't included on the CPU die itself is primarily about cost. CPU die space is significantly more expensive because of the manufacturing process required to make the very small features. It may also not be possible to manufacture the two on the same die, though I don't know enough about the details to give any ...


19

The appropriate standard solution is probably QSPI (also called QPI, or also SQI). It is somewhat an extension of the SPI interface, but uses four (quad, hence the Q in the acronym) data bits (IO0/IO1/IO2/IO3) instead of a single signal for each direction (MISO/MOSI). So the chips are very small (typically SO-8), and the interface is very efficient: you ...


18

Mask ROM. In Mask ROM, there is no reprogramming. Conceptually, 1's are directly connected to VCC and 0's are directly connected to ground with metalized areas in the construction of the IC. But you literally need to alter the design of the chip and make new chips to change it. So if you commit executable code to mask ROM and then find a bug, you have to ...


17

You can't really make assumptions about the program counter (PC) width from the memory address width. There have been many many different memory architectures historically, and new ones will undoubtedly be dreamed up. At a very basic level for the simplest of machine, the PC contains the memory address during instruction fetches, so is the same width as ...


17

You misunderstand what the heap is. The heap is the area where malloc gives you blocks of RAM dynamically at run-time. Your globally scoped, statically allocated variables & arrays are not 'on the heap'. If you're not using malloc or any of its variants in your program, you can quite safely set the heap size to 0.


Only top voted, non community-wiki answers of a minimum length are eligible