Questions about the behaviour of FlipFlops when the normal input setup or hold requrements are not respected, usually when launch and capture clocks are not synchronous.

When the D-input to a flop is not stable and in the relevant logic 0 or logic 1 voltage range at the time of the clock edge, the feedback paths within the flop can balance each other, and the output of the flop can (in the extreme case) remain at mid-rail until the subsequent clock edge.

This has a consequent effect on the following logic stages, so needs careful circuit design to manage the effects.