# Tag Info

113

Think about it. What exactly do you envision a "256 bit" processor being? What makes the bit-ness of a processor in the first place? I think if no further qualifications are made, the bit-ness of a processor refers to its ALU width. This is the width of the binary number that it can handle natively in a single operation. A "32 bit" processor can ...

73

The two killer reasons are yield, and heat. Yield. Every time you do a process step, you get less than 100% perfection. Let's say you get 99% perfection per step. In a process with 20 steps, you would be down to 82%. In a process with 1000 steps, you would be down to 43 ppm, 43 successful builds for every million wafers started. Heat. Our existing designs ...

67

See this extremely detailed account of the PC boot sequence: http://www.drdobbs.com/parallel/booting-an-intel-architecture-system-par/232300699?pgno=2 Since no DRAM is available at this point, code initially operates in a stackless environment. Most modern processors have an internal cache that can be configured as RAM to provide a software stack. ...

66

There are other factors that contribute to the speed. Memory: Actual performance is often limited by memory latency. Intel CPUs have large caches to make up for this. Microcontrollers usually don't. Flash memory is much slower than DRAM. Power consumption: This is often a big deal in embedded applications. Actual 200 MHz Intel CPUs consumed more than 10 ...

52

On PIC and dsPIC chips, I have observed the following causes of unexpected reset. Hardware: Reset pin driven low or floating. Check the obvious stuff first! ESD coupling into the reset pin. I've seen this happen when completely unrelated equipment gets turned on on the same desk. Make sure there's enough capacitance on the reset pin, possibly as much as 1 ...

49

First, as Keelan's comment and Turbo J's answer point out, the measurement was 113,093 Dhrystone MIPS not native MIPS. The Ivy Bridge microarchitecture of the i7 3630QM can only commit 4 fused µops per cycle, though it can begin execution of 6 µops per cycle. (The number of fused µops in a trace of code is roughly equal to the number of instructions; some ...

40

Wafers are extremely sensitive during manufacture, because if any dust or dirt particle settles on it between any process steps, then the following process steps will fail on the contaminated spot. Once manufacture is finished, and the chip receives its last layer, dust will no longer bother it. I would venture a guess that desktop CPUs which have thermal ...

34

Well, I don't know about 256 or 512 bit, but I've heard about a 1024 bit processor (I can't find it right now). The word is VLIW, for Very Long Instruction Word. So that's the instruction bus, not the data bus width. The advantages are that you can implement Instruction Level Parallelism (ILP) on a large scale. My first encounter with ILP must have been 20 ...

34

One use of NOP (or NOOP, no-operation) instruction in CPUs and MCUs is to insert a little, predictable, delay in your code. Although NOPs don't perform any operation, it takes some time to process them (the CPU has to fetch and decode the opcode, so it needs some little time do do that). As little as 1 CPU cycle is "wasted" to execute a NOP instruction (the ...

34

There are several factors: high performance micro-architectures use register renaming. That is, the number of physical registers is higher than the number of architecturally visible registers and they are able to track independent uses of them. doubling the number of registers does not double the performance. ISTR (from Computer architecture, A ...

32

An illustrative example or two may help here. Take a look at the following hypothetical circuit: simulate this circuit – Schematic created using CircuitLab Suppose to start both A and B are high (1). The output of the AND is therefore 1, and since both inputs to the XOR are 1, the output is 0. Logic elements don't change their state instantly - ...

32

All options are wrong. Maximum number of (unique) opcodes a processor can execute is not limited by bus width. Normally a 12+ bit CPU is designed to have one command per data word so that it can read most instructions in one go. So a normal CPU be engineered to a limit of 2^12 opcodes. Existing CPU architectures that have more than 2^12 = 4096 opcodes are ...

29

Neither: it can be considered a single-board computer where the main CPU is a system-on-chip.

28

"Bitness" of a microprocessor is usually defined in terms of size of the general purpose registers. The size determines how large numbers a processor can handle natively and how much memory it can access. 64bit numbers are enough for almost any algorithm and the amount of addressable memory (16 million terabytes) is enough for quite some time to come. There ...

28

Although you could do this whole thing with just an amplifier and a microcontroller (Arduino), as far as I can see, you want the analog option. I have tried to create a circuit that outputs the voice level on the microphone. The range is from 0V to 4V. However, you can upgrade it easily to 0V to 5V by just changing the OP-AMP. Now, let's go into it; First ...

26

A transistor (FET, in modern ICs) never switches instantly from full OFF to full ON. There is a period while it's turning on or off where the FET acts like a resistor (even when fully ON it still has a resistance). As you know, passing a current through a resistor generates heat ($P=I^2R$ or $P=\frac{V^2}{R}$). The more the transistors switch the more ...

25

A major underlying technical reason for the slow speeds is that cheap/small MCUs only use on-chip flash memory for program storage (i.e. they don't execute from RAM). Small MCUs generally don't cache program memory, so they always need to read an instruction from flash before they execute it, every cycle. This gives deterministic performance and #cycles/...

24

It's not the width of number it can store, it's the width it can work with in a single operation. Customarily (but not necessarily) this also has a degree of correlation to the width of native memory addressing, and thus the amount of storage which can be easily mapped without ugly workarounds such as segmentation or bank switching. Today's 32-bit cores ...

23

If the compiler writers put some effort into optimizing it for that target, it will at least make some use of the special DSP instructions / architecture. But for ultimate performance it will never be as good as hand-tuned assembly. It might be plenty good enough, though - depends on your application. Other alternatives include: Write the majority of ...

22

All current flow in anything that isn't a superconductor generates heat. In chips, it's mostly flowing in aluminium "metal" layers (why not copper? Nasty chemical interaction with other parts of the silicon, it turns out). What causes current to flow? Every time a transistor changes state, this can be modeled as a capacitor (the FET gate of the driven logic ...

22

Why do people ride a bicycle or a small motorbike, when you have a Formula 1 car? Surely it must be better to drive say 300 km/h and get everywhere instantly? To put it simply, there's no need to be faster than they are. I mean, sure there is a bit and faster microcontrollers do enable some things, but what are you going to do in say a vending machine that ...

21

First instructions are not necessarily "executed sequentially" even on a non-VLIW ISA, execution only needs to appear sequential. An in-order superscalar implementation can execute more than one instruction in parallel with another. To do this effectively the hardware for decoding instructions must be increased (widened), hardware must be added to ensure ...

21

A microprocessor: is typically found in a desktop PC or laptop and contains a CPU and an external memory interface plus various I/O buses to connect to the outside world such as SPI, I2C, UART, USB, LCD and others. A microprocessors will also have an external crystal to provide a clock. Most microprocessors have no read-only memory on the chip; instead ...

21

I feel a lot of these answers are not exactly hitting on the core question. The micro-controller has a clock simply because it executes (and is driven by) sequential logic. In digital circuit theory, sequential logic is a type of logic circuit whose output depends not only on the present value of its input signals but on the sequence of past inputs, the ...

21

Premature optimization is the root of all evil. - Donald Knuth When you find that you don't get enough performance from your code, profile your program first, find the bottlenecks, analyze your performance requirements, and only then start doing optimizations. Writing assembly code is last resort. My question is if I just program in C, wouldn't the ...

21

This is done using a device called a phase-locked loop, or PLL. Here is a block diagram of a basic PLL: simulate this circuit – Schematic created using CircuitLab The oscillator on the motherboard does not run at the CPU clock frequency, instead it runs at a frequency on the order of 100 MHz. This oscillator serves only as a known, stable reference ...

20

Most 8 bit CPUs have 16 bit address buses allowing them to address 64kbytes, precisely because 256 bytes really isn't enough to do very much! It just means they need to load two bytes instead of one, each time they need to load an address. Slightly slower but tolerable considering their size. (And yes there are many exceptions, mostly developed when 64k ...

20

If there is a single memory interface, there would be hardware to arbitrate between requests. Typically a processor would be given priority over I/O without starving I/O, but even with I/O always having priority the processor would have some opportunities to access memory because I/O tends to have lower bandwidth demands and to be intermittent. In addition, ...

20

It's always better to have your algorithm implemented in a higher-level language (which C is compared to assembly), even if you plan to implement everything in assembly in the end. chances are, you won't even need assembly. If the code generated by your compiler meets your design goals, your job is done. if not, you won't be starting your assembly coding ...

19

Actually crystal oscillators can easily go up to 10's of MHz. Above that in most cases a PLL (Phase Locked Loop) is used, which is an oscillator that is not very accurate in itself, but can be tuned (its frequency can be adjusted somewhat). The frequency of this high-frequency oscillator is divided by a suitable factor (dividing a signal by a power of 2 is ...

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