19 votes

what is triplication on fpga?

Triplication means (as noted) to make 3 of everything. It is used in space and safety critical designs, and data results are voted; a disagreement in the vote has to be designed such that the ...
Peter Smith's user avatar
  • 22.2k
4 votes
Accepted

Minimum FPGA clock frequency

In their datasheets, the recommended minimum operating frequency is 1.5MHz for the A3PE ProASIC3E chip. Actually, it's fIN_CCC that's specified as 1.5 MHz min in ...
TonyM's user avatar
  • 22.7k
3 votes

Maximum rate between ADC-FPGA link for Igloo 2 vs Max 10

The maximum clock for SRAM blocks of igloo 2 is 400MHz (Section 2.1.1 Product Brief) , and since many designs will use an SRAM block at some point, maybe that might be a good number to do a 'back of ...
Voltage Spike's user avatar
  • 81.3k
3 votes

Maximum rate between ADC-FPGA link for Igloo 2 vs Max 10

How can I find a ball park figure? Option 1: Build your design and synthesize it with appropriate constraints and see if timing closes. Option 2: Gain sufficient experience with a particular product ...
The Photon's user avatar
  • 129k
3 votes

How to transfer blocks of data into FPGA to aid in testing?

Last time I did this, it was a while ago, I used a Cypress FX2LP USB micro. It has a FIFO interface which is very FPGA friendly, and on the USB side it uses bulk transfers. No issues maxing out USB2 ...
bobflux's user avatar
  • 75.9k
2 votes

Why is there a need for an eNVM and an eSRAM in the same SoC FPGA

eSRAM is likely a lot faster, and as it is SRAM it can be written an unlimited number of times. Think of the eNVM as the hard drive/SSD and the eSRAM as the RAM.
alex.forencich's user avatar
2 votes

Why is there a need for an eNVM and an eSRAM in the same SoC FPGA

eNVM is nonvolatile and has a limited number of write cycles. eSRAM is volatile and has an effectively infinite number of write cycles. (Probably much faster, too.) A typical application needs both ...
Dave Tweed's user avatar
  • 172k
2 votes

How does Flash*Freeze reduce power consumption in Microsemi FPGAs?

The Microsemi Igloo Low Power design guide includes a flowchart on page 9, describing the entry process and all of its side effects. In particular: FDDR memory is placed into a self-refresh state and ...
nanofarad's user avatar
  • 19.4k
2 votes
Accepted

Smartfusion2 Programmer Error

After talking to Microsemi tech support the issue seems to be the following (Taken from the ER096 Errata document ): For the Revision 0 of the M2S090 and M2S150 devices, the eNVM needs to contain ...
EpicFoodCartDestroyer's user avatar
2 votes

Ethernet Auto Negotiation Timeout

I seem to be facing an issue where the auto-negotiation is timing out. Auto-negotiation is typically handled directly by the PHY. In every chip I have encountered, it should happen automatically ...
user4574's user avatar
  • 12.1k
2 votes
Accepted

Program FPGA without JTAG?

If you want to program the FPGA directly, such as when you are doing development work, you will use JTAG. If you want to program an FPGA that uses external memory (which was the norm until recently) ...
jwh20's user avatar
  • 7,902
2 votes

Is it possible to write an "interconnect" in VHDL by hand?

Yes. One can generally make anything that's auto-generated by hand. It will usually just take longer than inputting some parameters into an existing tool. In order to write an automation tool that ...
user4574's user avatar
  • 12.1k
2 votes
Accepted

Is there a reason to have different files or entities with same name in FPGA project?

Is it a good practice to have multiple entities in same file? Generally not, unless they're very closely related and will never need to be used separately. Very rare IME. What if entity and ...
Dave Tweed's user avatar
  • 172k
2 votes

HLS like programming on Actel devices

There is a tool for working on High level synthesis and write C like code that gets transformed to verilog/vhdl code. The tool is called SmartHLS by Microsemi. Smart HLS user guide It is eclipse based ...
abunickabhi's user avatar
2 votes
Accepted

Microchip FPGA Internal Short Circuit

The unused I/Os being weakly pulled up do not cause any issue. Please look at the below document https://www.microsemi.com/document-portal/doc_download/129992-hb-proasic3-e-sso-and-pin-placement-...
abunickabhi's user avatar
1 vote

Problem with back annotated netlist signals naming for simulation purposes in Modelsim

Assuming the main test bench is labeled as 'top_entity_tb', the following methodologies can be applied First method Requires using the ModelSim GUI. Needs steps listed below Go to top level testbench ...
nanoeng's user avatar
  • 171
1 vote

Error message vsim-3171 keeps popping up in Modelsim DE 2021.1 even though it was solved in Modelsim ME 10.2c

The issue associated to vsim-3171 goes away after the work library is refreshed as shown below vlog -work work_lib -refresh -force_refresh
nanoeng's user avatar
  • 171
1 vote

Libero does synthesis again before programming the device

There are two potential ways to correct the issue. Create a script that after running all the required steps to generate a config. file (synthesis, place & route, and config. file generation) ...
nanoeng's user avatar
  • 171
1 vote

Why program for MI-V bigger than 64 kB does not build properly?

I have to explain this, for I would need understanding of the readers. I may not be able to answer it at once, since I have passed that part of process some time ago, even for the current project. I ...
jay's user avatar
  • 3,831
1 vote
Accepted

FPGA simulation with crystal oscillator what to do with XTL input?

My understanding of the description is that for simulation you feed XTL with a signal from your testbench corresponding to the frequency of your crystal to allow ...
Tom Carpenter's user avatar
1 vote

Program FPGA without JTAG?

We also needed to update the firmware without opening the products. Now we use this remote programmer from FPGA Cores: The programming is done over Ethernet and you need to add one of these Ethernet ...
Holminge's user avatar
  • 149
1 vote

Program FPGA without JTAG?

Present (series 7) Xilinx FPGAs support a number of methods to load the bitstream: Master-Serial configuration mode Slave-Serial configuration mode Master SelectMAP (parallel) configuration mode (x8 ...
hacktastical's user avatar
  • 52.9k
1 vote

Ethernet Data Transfer (ARM M3-Cortex to PC)

Is there anyway I could ping the device from my laptop? Ping (via IPv4) requires ARP and that you have either manually set up IP addresses or use DHCP. There is "arping", but I don't ...
Turbo J's user avatar
  • 10.1k
1 vote

which interface to use TBI, GMII or MII? (FPGA)

Well, what Ethernet PHY are you using? Pick an Ethernet PHY, then implement the interface that the PHY wants. Most likely this will be MII or GMII, depending on the speed. Edit: according to the ...
alex.forencich's user avatar
1 vote
Accepted

Active Low LED and Active Low Switch behavior on FPGA counter-intuitive

(note: I am using the verilog operators in this post, but most reference materials you find will probably use other notation) So what am I missing here ? For AND and OR we have De-morgans theorem <...
Peter Green's user avatar
  • 22.1k
1 vote

24-bit binary to 32-bit bcd

You need to write a testbench to go with your functional code. This should drive the inputs, and you should check the outputs match what you expect. I can see ...
awjlogan's user avatar
  • 7,929
1 vote

Is Microsemi Libero supposed to have many arithmetic cores inside its catalogue?

Microsemi confirmed that all those cores I mentioned above do not exist. I am working with IGLOO2 platform. They said there is a divider core in alpha or beta testing but not released yet. So we are ...
gyuunyuu's user avatar
  • 2,023
1 vote
Accepted

How to "Pull Down" LVDS input in FPGA

Under the set_io command (page 282, specifically), it lists that only certain IO standards can take pullups/pulldowns. Newer versions of this guide list what standards can take pullups/pulldowns, but ...
Drew's user avatar
  • 108

Only top scored, non community-wiki answers of a minimum length are eligible