19

Triplication means (as noted) to make 3 of everything. It is used in space and safety critical designs, and data results are voted; a disagreement in the vote has to be designed such that the erroneous result circuit is reset. For this to work within a single device, partial reconfiguration in the FPGA is required. The reason this is necessary in SRAM ...


6

You might not like this answer, but an easy way to get into FPGAs is just to switch to a board that has better support so you can learn the fundamentals. For example, with $120 you can do what I did and learn on the Papilio Pro board (it's a Xilinx part, not sure if you MUST use Microsemi). You can learn the basics of VHDL, what steps are included to get a ...


3

The maximum clock for SRAM blocks of igloo 2 is 400MHz (Section 2.1.1 Product Brief) , and since many designs will use an SRAM block at some point, maybe that might be a good number to do a 'back of the napkin' calculation with that would give you a max number, the real number could be substantially lower than that. But there is no way to tell unless you ...


3

How can I find a ball park figure? Option 1: Build your design and synthesize it with appropriate constraints and see if timing closes. Option 2: Gain sufficient experience with a particular product family to have a good idea how complex a design can be run at a given frequency. That said, if the I/O pins can handle a given data rate, there are techniques ...


3

Last time I did this, it was a while ago, I used a Cypress FX2LP USB micro. It has a FIFO interface which is very FPGA friendly, and on the USB side it uses bulk transfers. No issues maxing out USB2 bulk bandwidth with python/libusb. Pros: 480 Mbps is great if you need it, bulk USB does the error correction, and the chip is not difficult to use. python/...


3

This is an old question, but I couldn't find this information anywhere so I think it's helpful to add it here! In Libero you can go to File -> Export Script File... and export a Tcl script with the commands that have been run in your current project - importing files, creating IP etc. If you create an IP core and then export the script file, you will see ...


2

eSRAM is likely a lot faster, and as it is SRAM it can be written an unlimited number of times. Think of the eNVM as the hard drive/SSD and the eSRAM as the RAM.


2

eNVM is nonvolatile and has a limited number of write cycles. eSRAM is volatile and has an effectively infinite number of write cycles. (Probably much faster, too.) A typical application needs both kinds of memory.


2

As there are no answers to your question yet, allow me to describe a hack that I would use myself. Hopefully it attracts attention to the question for other answers. I am a Linux user myself, but read on there are some Windows pointers once you read through the Linux part. Do browse through the Linux paragraph first though. As a generic solution to this ...


2

The Microsemi Igloo Low Power design guide includes a flowchart on page 9, describing the entry process and all of its side effects. In particular: FDDR memory is placed into a self-refresh state and its clock source is stopped. SERDES PHYs, PMAs, and PLLs are placed into the lowest power state (low-power mode for PHYs/PMAs and power-down for PLLs) MDDR ...


2

I seem to be facing an issue where the auto-negotiation is timing out. Auto-negotiation is typically handled directly by the PHY. In every chip I have encountered, it should happen automatically without any setup as long as... The chip has power You aren't holding the chip in reset. The +/- in each differential pair is not swapped The TX and RX pairs are ...


2

Yes. One can generally make anything that's auto-generated by hand. It will usually just take longer than inputting some parameters into an existing tool. In order to write an automation tool that generates code, the programmer has to know how to write that code by hand. Otherwise they wouldn't be able to write out the detailed instructions that form the ...


2

Is it a good practice to have multiple entities in same file? Generally not, unless they're very closely related and will never need to be used separately. Very rare IME. What if entity and architecture are to be kept in different files? What should the files be named in that case? I have done some projects like that. It becomes useful if some of the code ...


1

I have to explain this, for I would need understanding of the readers. I may not be able to answer it at once, since I have passed that part of process some time ago, even for the current project. I would be very happy to yield if someone right at the position come in. You are in a serious area that EEs encounter when sofis complain hardware not working. ...


1

My understanding of the description is that for simulation you feed XTL with a signal from your testbench corresponding to the frequency of your crystal to allow simulating different frequencies. Then continue to use CLKOUT in your design as if you had a real crystal. For synthesis, either XTL is fed out of the top level and assigned to the correct pin, or ...


1

We also needed to update the firmware without opening the products. Now we use this remote programmer from FPGA Cores: The programming is done over Ethernet and you need to add one of these Ethernet cores. It works very good and we can also do remote debugging. We mostly use Artix from Xilinx.


1

Present (series 7) Xilinx FPGAs support a number of methods to load the bitstream: Master-Serial configuration mode Slave-Serial configuration mode Master SelectMAP (parallel) configuration mode (x8 and x16) Slave SelectMAP (parallel) configuration mode (x8, x16, and x32) JTAG/boundary-scan configuration mode Master Serial Peripheral Interface (SPI) flash ...


1

If you want to program the FPGA directly, such as when you are doing development work, you will use JTAG. If you want to program an FPGA that uses external memory (which was the norm until recently) then you need only program the external memory device (which generally have their own programming protocols not using JTAG) and then reset the FPGA so that it ...


1

Is there anyway I could ping the device from my laptop? Ping (via IPv4) requires ARP and that you have either manually set up IP addresses or use DHCP. There is "arping", but I don't remember OTOH if there is a windows port for this tool. Both IPv4 and IPv6 are significanly complex protocols, a bit too much for a post here. Use of exisiting ...


1

After talking to Microsemi tech support the issue seems to be the following (Taken from the ER096 Errata document ): For the Revision 0 of the M2S090 and M2S150 devices, the eNVM needs to contain valid Cortex-M3 code. By default, SmartFusion2 parts are shipped with a default boot-up program stored at the eNVM address 0x60000000. If this default program is ...


1

(note: I am using the verilog operators in this post, but most reference materials you find will probably use other notation) So what am I missing here ? For AND and OR we have De-morgans theorem A | B === ~((~A)&(~B)) A & B === ~((~A)|(~B)) For XOR the following is true (not sure if this identity has a name) A ^ B === (~A)^(~B) Your buttons and ...


1

You need to write a testbench to go with your functional code. This should drive the inputs, and you should check the outputs match what you expect. I can see plenty of things that might be wrong in this, but you should try to write test cases (and drivers) and check the results. As a beginner, it can be difficult to keep track of what is happening ...


1

Well, what Ethernet PHY are you using? Pick an Ethernet PHY, then implement the interface that the PHY wants. Most likely this will be MII or GMII, depending on the speed. Edit: according to the schematic for your board (https://www.digikey.com/eewiki/download/attachments/64422068/DIGIKEY%20MAKER%20KIT%20REVA1_0_20170606.pdf?version=1&modificationDate=...


1

Under the set_io command (page 282, specifically), it lists that only certain IO standards can take pullups/pulldowns. Newer versions of this guide list what standards can take pullups/pulldowns, but aren't for the ProASIC3 specifically. Unfortunately, LVDS isn't one of the standards that can take pullups/pulldowns.


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