5
votes
Accepted
Ethernet Transmission with one MAC and Multiple PHYs
Typically, a set of MII lines are connected from the MAC to a single PHY. The reason for multiple addresses for MDIO is for SOCs that contain multiple MAC modules and for switch chips. The MII from ...
- 8,374
3
votes
Media Independent Interface signals
The tx clock is generated locally via the phy and a crystal oscillator whereas the rx clock is recovered from the incoming data.
The wikipedia link you provided tells you this.
- 6,678
3
votes
Embedded Ethernet Solution w/ PoE+; SPI or MII?
Having looked at both options, I ended up implementing an MII interface
Firmware wise, is MII or SPI more difficult to implement, or are they
the same difficulty?
The MII is more difficult to ...
- 88.8k
2
votes
Accepted
How should I connect two MII devices back to back?
Just look at the data directions on the pins.
Generally, you only connect outputs to inputs, so...
The short answer for these two chips is that RX connects to RX and TX connects to TX. Also the ...
- 12.5k
1
vote
Accepted
Media Independent Interface signals
You need a clock to transmit data, and you need a clock to receive data from another transmitter.
Because each device transmits with the clock it generates, you can't use your own transmit clock for ...
- 172k
1
vote
Lan9500 to Switch (KSZ8795) MII wiring
You need to consider that the data sheets should describe what type of interface is on each device. (i.e. if TX is an output from a particular device or an input). If that is not fully apparent from ...
- 57.9k
1
vote
Accepted
Ethernet Phy Rx developed in a FPGA to send data to an ethernet Mac
First, what interface are you using? You said MII, but MII uses tx_en/tx_er or rx_dv/rx_er instead of tx_ctl/rx_ctl. Unless you're actually using RGMII, which muxes those two into one signal on ...
- 41.6k
1
vote
How to connect two Ethernet switch ICs together using MII Interface
Q1: It's difficult to say with only the datasheet. There might be application notes about this. If you want the largest amount of RJ45 copper PHY ports, P4 should be left with UTP, so port 5 is ...
- 172k
1
vote
MDIO bus pull-ups
There is no need for multiple pull-ups on MDIO as that would amount to a single pull-up resistance anyway. You would look at MAC or PHY requirements for pull-up resistance and take a value that is ...
- 172k
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