6 votes
Accepted

VHDL simulation shows 'X' for input

You have multiple drivers for the signals A and B here: ...
Martin Zabel's user avatar
  • 1,296
5 votes

how slow are modelsim free licences?

ModelSim PE Student Edition limits the user to 10,000 lines of executable code. The performance of your code up to this capacity is 30% that of the full version (the full version is 3.3x faster). The ...
Darius's user avatar
  • 1,196
5 votes
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Why is my 8-bit counter only counting until 127?

In the Modelsim waveform display, you need to right-click on the output signal and change the data representation to unsigned. It's currently interpreting the 8-bit value as a signed integer.
Dave Tweed's user avatar
  • 172k
4 votes
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How to assign a hexadecimal value to integer type in VHDL?

VHDL supports arithmetic values but it has to know if they are signed or unsigned. I recommend using the numeric_std library to support these types. VHDL is strongly typed. For your first question, ...
Claudio Avi Chami's user avatar
4 votes
Accepted

ModelSim: Why can't I see generics in simulation?

Generics and constant values can be seen in the objects window of QuestaSim/ModelSim. You could also drag them into the waveform, but they wont change ... (clickable)
Paebbels's user avatar
  • 3,907
4 votes
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What is the standard way to represent fixed point numbers in VHDL?

If You'd like to implement fixed point arithmetics in synthesizable VHDL you have two ways: Do It Yourself. It's rather hard method, but it may depend on quantity and complexity of equations You want ...
Jakub Rakus's user avatar
  • 2,235
4 votes
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Export Modelsim waveforms as image for printing

in a form where they can look decent when printed is a very subjective statement. Moreover, you can't really customize MSIM wave editor to display things very differently. Considered your question is ...
vaugs's user avatar
  • 191
4 votes

Why does modelsim show St0, St1 & Pu0 for value of logic signal?

I am myself a beginner so this won't answer your question entirely, but maybe you can look at this table from User's manual Table: P.S. I also realize this is an old post, but anyway, whoever lands ...
Giorgi Aptsiauri's user avatar
4 votes
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This model of a D-Flip flop with Enable not working as expected

In your first code sample, you have a low active reset (if (~Reset) D <= 0). And in the testbench you hold Reset low for most ...
The Photon's user avatar
  • 129k
4 votes
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How to set QuestaSim/ModelSim to print time value in arbitrary unit?

Use to_string (vhdl-2008) instead of 'image and specify the time units. Hence, for ns it is: ...
Jim Lewis's user avatar
  • 923
3 votes
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Unexpected behaviour in Altera clock crossing FIFO

I've designed a few FIFOs and the truth is that there is no reason for the FIFO to output zero when empty. Think of a FIFO as having two pointers: a write, and a read pointer. When you push data it is ...
user110971's user avatar
  • 6,117
3 votes
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Why can't I connect a std_logic_vector signal to a port of type signed or unsigned

Although in your example unsigned and signed are both arrays of the same element type ...
scary_jeff's user avatar
  • 1,987
3 votes
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Is it possible to have multiple wave windows in ModelSim?

You can create a new Wave window with the following command: view wave -new The new windows have incremental name's, like "Wave1", "Wave2", .. but you can give a ...
PKo's user avatar
  • 173
3 votes

Quartus, Modelsim, VHDL - Viewing Internal Signals

From Modelsim, you should easily be able to click on the module that you want (Circle 1) and in Objects window (Circle 2) you will be able to see the signals within that module and you can then easily ...
bFig8's user avatar
  • 141
3 votes

Aggregate of 2 vectors in VHDL

Use the VHDL-2008 Library in ModelSim and your error is resolved. VHDL-93/2002 packages don't support aggregating vectors like the way you have expressed.
Mitu Raj's user avatar
  • 10.9k
3 votes

Work library is empty after compiling Verilog source file in Modelsim

From your screenshot it seems that you haven't saved the file - are you sure you saved your file before compiling? Else ModelSim might be simply compiling an empty file - which would, of course, yield ...
koalag's user avatar
  • 264
3 votes
Accepted

Verilog output is hiZ in testbench

You declared the out signal as a wire in your testbench, and you connected it to the out <...
toolic's user avatar
  • 7,778
3 votes

Verilog code for construction of 4x16 decoder using 3x8 decoder

Well, first off your input needs to be 4 bits instead of 3. Second, you need to use the 4th bit to generate the enables for the two decoders.
alex.forencich's user avatar
3 votes
Accepted

Errors in VHDL code

Your entity signals clk, load and reset should be of type ...
po.pe's user avatar
  • 2,546
3 votes
Accepted

Where did I code my multiplier wrong?

There is nothing wrong in it. You are multiplying two unsigned numbers in your Verilog code. So you will get an unsigned result. The valuesx, ...
Mitu Raj's user avatar
  • 10.9k
2 votes
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VHDL - Issue with simulation of testbench - Modelsim PE Student 10.4

There are some typical errors that you should understand and avoid first. When creating your process instantiating your register you didn't specify any sensitivity list. (If you don' t know what it ...
A. Kieffer's user avatar
2 votes

Compile error in testbench with UVM (mtiRnm library)

The solution was to delete the modelsim.ini file in the compilation folder...don't know what happened, but it works.
arandomuser's user avatar
2 votes

How to speed up Modelsim simulation

This is a really common issue for all FPGA developers. Here are my advice (there are probably many other). First you can decide to watch only few signals, so that the calculation will run faster. You ...
A. Kieffer's user avatar
2 votes

Histogram Graph in ModelSim Simulator

AFAIK, the only graphing that Modelsim can do internally is to show the value of a multi-bit bus as an "analog" value. Therefore, one thing you could do is create a module for your testbench that ...
Dave Tweed's user avatar
  • 172k
2 votes

Open a picture and read its Pixel Values

You can save your image as a PPM image (Wiki). Then you can load or save it as text file
Botnic's user avatar
  • 2,275
2 votes
Accepted

Modelsim: Force string

If you open the command reference manual by going to 'Help > Documentation - PDF Bookcase', you can find the complete syntax for this command. It would be helpful if you included the error message ...
scary_jeff's user avatar
  • 1,987
2 votes

Why does Modelsim say that VHDL shared variables must be protected?

Non-protected shared variables are fine if you know what you are doing, and I would personally prefer if Modelsim did not produce the warning. (It is not present if you compile for VHDL-93.) In your ...
pc3e's user avatar
  • 253
2 votes
Accepted

Can VHDL read binary files i.e non text files?

Firstly, hex file are text files. Secondly, I have found it easier to write scripts to parse the external files in VHDL, than to use VHDLs limited text processing capabilities. Another option you ...
user110971's user avatar
  • 6,117
2 votes
Accepted

How to model devices external to FPGA in a testbench?

If you are to use an external SRAM in your FPGA platform, then you need not only the "cycle accurate", but also (mostly) "timing-accurate" model, if you want something to work. The timing depends on ...
Ale..chenski's user avatar

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