9 votes
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How do I debug red signals in ModelSIM?

Nice to see a proper testbench and code that actually matches the question for a change... There are two easy ways for a signal to be corrupted: drive it from several signal sources don't drive it ...
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  • 66.1k
6 votes
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VHDL simulation shows 'X' for input

You have multiple drivers for the signals A and B here: ...
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  • 1,256
5 votes

how slow are modelsim free licences?

ModelSim PE Student Edition limits the user to 10,000 lines of executable code. The performance of your code up to this capacity is 30% that of the full version (the full version is 3.3x faster). The ...
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  • 1,188
5 votes
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Why is my 8-bit counter only counting until 127?

In the Modelsim waveform display, you need to right-click on the output signal and change the data representation to unsigned. It's currently interpreting the 8-bit value as a signed integer.
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  • 165k
4 votes
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ModelSim: Why can't I see generics in simulation?

Generics and constant values can be seen in the objects window of QuestaSim/ModelSim. You could also drag them into the waveform, but they wont change ... (clickable)
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  • 3,807
4 votes
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Does modelsim support shift right arithmetic in verilog?

It does, however you need to make temp a signed value and do not specify the range when using the arithmetic shift. Specifying the range in the arithmetic shift ...
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  • 4,110
4 votes
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What is the standard way to represent fixed point numbers in VHDL?

If You'd like to implement fixed point arithmetics in synthesizable VHDL you have two ways: Do It Yourself. It's rather hard method, but it may depend on quantity and complexity of equations You want ...
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  • 2,215
4 votes
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This model of a D-Flip flop with Enable not working as expected

In your first code sample, you have a low active reset (if (~Reset) D <= 0). And in the testbench you hold Reset low for most ...
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  • 121k
4 votes

How to set QuestaSim/ModelSim to print time value in arbitrary unit?

Use to_string (vhdl-2008) instead of 'image and specify the time units. Hence, for ns it is: ...
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  • 745
3 votes
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TEXTIO : Read past end of file in ModelSim Simulation

Sorry to bypass all the comments but to me the solution to this doesn't really depend on anything. You have not got if (rising_edge(RST)) then <ROM init loop>,...
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  • 1,947
3 votes
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Clock Generation in modelsim

It sounds like your simulation resolution is set to 1 ns, in which case any any wait statements will be rounded down to the nearest nanosecond.
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  • 1,947
3 votes

What does delta stands for in ModelSIM?

A delta is a small (infinitesimal) time increment that is used during simulation. The number listed is the number of these time steps that were taken to resolve the signal timing. You can suppress ...
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  • 29.6k
3 votes

VHDL Overmapping and Time Constaint issues in Xilinx-ISE

From the timing report you attached, the critical path has 378 levels of logic in it. I can't emphasize enough how much 378 levels is, from the project I'm working on (video compression), my critical ...
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3 votes
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How to assign a hexadecimal value to integer type in VHDL?

VHDL supports arithmetic values but it has to know if they are signed or unsigned. I recommend using the numeric_std library to support these types. VHDL is strongly typed. For your first question, ...
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3 votes
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Why can't I connect a std_logic_vector signal to a port of type signed or unsigned

Although in your example unsigned and signed are both arrays of the same element type ...
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3 votes
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Unexpected behaviour in Altera clock crossing FIFO

I've designed a few FIFOs and the truth is that there is no reason for the FIFO to output zero when empty. Think of a FIFO as having two pointers: a write, and a read pointer. When you push data it is ...
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  • 5,924
3 votes
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Export Modelsim waveforms as image for printing

in a form where they can look decent when printed is a very subjective statement. Moreover, you can't really customize MSIM wave editor to display things very differently. Considered your question is ...
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  • 171
3 votes

Quartus, Modelsim, VHDL - Viewing Internal Signals

From Modelsim, you should easily be able to click on the module that you want (Circle 1) and in Objects window (Circle 2) you will be able to see the signals within that module and you can then easily ...
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  • 141
3 votes

Aggregate of 2 vectors in VHDL

Use the VHDL-2008 Library in ModelSim and your error is resolved. VHDL-93/2002 packages don't support aggregating vectors like the way you have expressed.
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  • 10.5k
3 votes
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Verilog output is hiZ in testbench

You declared the out signal as a wire in your testbench, and you connected it to the out <...
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  • 2,836
3 votes

Verilog code for construction of 4x16 decoder using 3x8 decoder

Well, first off your input needs to be 4 bits instead of 3. Second, you need to use the 4th bit to generate the enables for the two decoders.
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3 votes
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Errors in VHDL code

Your entity signals clk, load and reset should be of type ...
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  • 2,445
3 votes
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Where did I code my multiplier wrong?

There is nothing wrong in it. You are multiplying two unsigned numbers in your Verilog code. So you will get an unsigned result. The valuesx, ...
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2 votes
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Is it possible to have multiple wave windows in ModelSim?

You can create a new Wave window with the following command: view wave -new The new windows have incremental name's, like "Wave1", "Wave2", .. but you can give a ...
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  • 163
2 votes

Using generic packages with protected type in Modelsim 10.xy

With the help of a nice guy from the Mentor Graphics Forums we found out that it is not supported by this Modelsim version. The results for different Modelsim versions are: Modelsim 10.0a: Does not ...
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  • 373
2 votes
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How to Add the Xilinx Library to Modelsim?

compile UNISIM libraries by runnin compxlib and following wizard. then in your modelsim, library pane add new library. after that add library from existing library ...
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  • 392
2 votes

VHDL Overmapping and Time Constaint issues in Xilinx-ISE

The right/left rotate operator is simply a mux tree, so the real reasons for this could be unrelated to the ror/rol: you may be connecting the modules in a wrong or partially recursive way, with not ...
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2 votes

Running UVM example on MODELSIM - ALTERA 10.1d

Based on the error message, you are not including the UVM source in your compile. Some tools have UVM built-in that can be enabled with the -uvm argument at compile ...
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  • 4,110
2 votes
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Cursor (waveform) reading not the same with transcript window

That looks correct. The values in the transcript window are the signal levels 'leading in' to the clock edge. This constitutes an ideal setup time. With the cursor positioned directly on a clock ...
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