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You need to save the waveform/dataset as a .wlf file. To tell Modelsim to capture all signal values in the design you can do a log -r /*. Afterwards you can open up the specific waveform/dataset .wlf either through the GUI or by typing vsim -view <some_name>.wlf in the console. Have a look in the ModelSim/QuestaSim user manual under 'Saving a ...

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External Control of a ModelSim Simulation Via Unix Named Pipes Abstract: In this thesis, we present a method of controlling a ModelSim simulation via an external program. Communication between ModelSim and the external program is accomplished by using Named Pipes ("FIFOs"), which appear as normal files to each application. The main difference ...

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Nice to see a proper testbench and code that actually matches the question for a change... There are two easy ways for a signal to be corrupted: drive it from several signal sources don't drive it from any Now A11 remains 'U' throughout, suggesting it has no driver. While A1 alternates between valid and 'X' invalid values, suggesting it has more than one ...

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It has to do with what can be easily evaluated at elaboration time, formally, what is called a "locally static expression". This is an obscure looking rule, but it deserves some thought - eventually it does make some sense, and your simulator is quite correct in alerting you by generating non-obvious results. Now, temp(1) can be evaluated at compile time (...

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You have multiple drivers for the signals A and B here: A<="0000"; B<="0000"; and here: PROCESS BEGIN WAIT FOR 23 NS;A(0)<='1';B(0)<=NOT B(0); WAIT FOR 23 NS;A(3)<='1';B(3)<='1'; WAIT FOR 23 NS;A(2)<='1';B(2)<='1';A(0)<='0';B(0)<='0'; WAIT FOR 23 NS;A(1)<='1';B(3)<='0';A(0)<='1';B(0)<='1'; WAIT FOR 23 ...

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You might want to look at Cocotb. It's a Python based co-simulation library, one of the design goals was to enable the methodology you describe, easily simulating un-modified production software and RTL. There's an example in the repository of running unmodified ping command against a simulation and a tutorial walking through the code. For user-space ...

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If the memory you are simulating can fit into the ram of the workstation then using a fixed-size storage is the easiest to use. But as you have seen, signals are much more expensive compared to variables. This difference is related to the discrete event simulation model that VHDL is based on. A signal assignment schedules a transaction at a given point in ...

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ModelSim PE Student Edition limits the user to 10,000 lines of executable code. The performance of your code up to this capacity is 30% that of the full version (the full version is 3.3x faster). The student edition can still run code past the 10,000 line capacity, but it slows the performance down dramatically to 1% of the full version (the full version is ...

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I don't think you can use Ibis in Modelsim... For Ibis, you need a signal integrity simulator such as Hyperlynx. But its purpose is to ensure the integrity of high speed signals, including the effects of PCB traces on waveforms. If you are modelling the digital interactions between your FPGA and the TI chip, you need a "bus functional model" for that chip ...

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First of all it would be good to know which version of Modelsim/ISE you are using. In general the Xilinx simulation libraries have to be compiled. Only ISim ha pre-compiled binaries. The compilation can be done with the command-line tool compxlib that is supplied with ISE. The usage is described in Command Line Tools User Guide (v14.4) - the link points to ...

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It does, however you need to make temp a signed value and do not specify the range when using the arithmetic shift. Specifying the range in the arithmetic shift casts a unsigned value. reg signed [31:0] temp; always @* begin temp = 32'hfff00fff; result[31:0] = temp >>> shamt[4:0]; end Alternatively, you can cased it as signed with $signed ... 4 Generics and constant values can be seen in the objects window of QuestaSim/ModelSim. You could also drag them into the waveform, but they wont change ... (clickable) 4 If You'd like to implement fixed point arithmetics in synthesizable VHDL you have two ways: Do It Yourself. It's rather hard method, but it may depend on quantity and complexity of equations You want to implement. Generally every "variable" should have two parts (integral and fractional) made of std_logic_vectors. Of course You have to implement basic (... 3 IEEE Std 1364-1995 § 14.1.1.4 "Unknown and high impedance values" and IEEE Std 1800-2012 § 21.2.1.4 "Unknown and high-impedance values": If all bits in a group are at the unknown value, a lowercase x is displayed for that digit. If all bits in a group are at a high-impedance state, a lowercase z is printed for that digit. If some, but ... 3 There are no simulator commands that I'm aware of to invert a signal. However, if you are doing the force from within the Verilog source, you should simply be able to do this: force path.to.signal = ~path.to.signal; If you are forcing it from the simulator, you can probably do the equivalent of the above statement in TCL. You would need to get the current ... 3 According to Altera's knowledge base, it's a bug in their simulation library, which incorrectly has the parameter names defined only in lower case (it should, apparently, be able to accept either). http://www.altera.co.uk/support/kdb/solutions/rd04192000_5867.html Searching directly for the error message didn't turn it up, because the text of the error ... 3 Your code will not work. In verilog, a 'z' at the input of a gate transforms to an 'x' on the output of the gate. An 'x' at the input of the gate also translates to an 'x' on the output of the gate. Therefore your code reduces to if(wr_req & !cam_busy & X & X & X) The value of (something & X) can be either 0, or X, and in both cases ... 3 Xilinx generally supply precompiled versions of their Unisims libraries for Modelsim, along with installation instructions. The Xilinx website "support" pages ought to have more information specific to your Modelsim and ISE versions (whatever versions those are) Unfortunately I can't provide more specific help : the library names you mention suggest you ... 3 A delta is a small (infinitesimal) time increment that is used during simulation. The number listed is the number of these time steps that were taken to resolve the signal timing. You can suppress these with the -NODELTA switch on the command line. This is telling you that the signal is changing after the main time tick event. To know what value is ... 3 Simulation cycles are characterized by those that result in the advancement of simulation time and those that don't. Those that don't are known as delta cycles. From a simulation cycle resulting from the advancement of simulation time assignment to a signal without a delay (e.g. after, wait for) will cause a delta cycle as the next simulation cycle without ... 3 From the timing report you attached, the critical path has 378 levels of logic in it. I can't emphasize enough how much 378 levels is, from the project I'm working on (video compression), my critical path is only 8 levels deep. This is part of your problem, not only the propagation delays are enormous from going trough so many LUTs, ISE has a lot of problem ... 3 It sounds like your simulation resolution is set to 1 ns, in which case any any wait statements will be rounded down to the nearest nanosecond. 3 Sorry to bypass all the comments but to me the solution to this doesn't really depend on anything. You have not got if (rising_edge(RST)) then <ROM init loop>, but if (RST = '1') then <ROM init loop>. Since you have CLK in the sensitivity list for the process, any change in CLK while RST is high, will cause the loop to run again, causing the ... 3 Although in your example unsigned and signed are both arrays of the same element type std_logic, this is not the same as a subtype. A subtype is when one type is a limited subset of another type, for example: subtype my_type is std_logic_vector(3 downto 0); subtype eight_bit_int is integer range 0 to 255; A feature of a subtype is that it can be ... 3 I've designed a few FIFOs and the truth is that there is no reason for the FIFO to output zero when empty. Think of a FIFO as having two pointers: a write, and a read pointer. When you push data it is written to the write pointer address, and the write pointer is incremented. When you pop the FIFO the read pointer increments. The output of the FIFO is the ... 3 From Modelsim, you should easily be able to click on the module that you want (Circle 1) and in Objects window (Circle 2) you will be able to see the signals within that module and you can then easily drag the signals you want to the Wave window. You shouldn't have to create IO ports just to view the signals on Modelsim. 3 Use the VHDL-2008 Library in ModelSim and your error is resolved. VHDL-93/2002 packages don't support aggregating vectors like the way you have expressed. 3 In your first code sample, you have a low active reset (if (~Reset) D <= 0). And in the testbench you hold Reset low for most of the simulation. As expected this results in D being 0. In your second code sample you have a high-active reset (if (reset) q <= 0 ) which will naturally behave differently. 2 If you don't get a violating in timing analysis, but do in simulation, your timing analysis is likely incomplete. Revisit clock crossing and TIG (ignore) in particular. See Xilinx answer 38348 for more details on TIG. 2$dumpvars (1, testbench.gcm_tb); is your problem. To get all the lower-level signals you need \$dumpvars (0, testbench.gcm_tb);

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