New answers tagged modelsim
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One of the best pieces of advice my FPGA mentor gave me was
"let the tool do the thinking for you"
At the end of the day, the tool is going to be converting the code you write into boolean algebra in any case. You don't need to do its job for it. There are many many ways to produce the same result in HDL. Choose the way that makes sense to you, and is ...
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Write a process, write a case, just latch the information you need in your process:
p_main: process(clk, reset_n)
type t_nible_state is (firstnible, secondnible);
variable r_nible_state : t_nible_state;
variable r_latchednible : std_logic_vector(7 downto 0);
variable r_latchedparity : std_logic;
variable nibletosend : std_logic_vector(3 downto 0)...
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I have not tried this yet, but how about something like:
d_full_s <= '1';
wait for 5 ms;
d_full_s <= '0';
You may also need to set all of the strobes to zero early near the beginning as part of your reset, to prevent erroneous values.
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