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There is a non-documented option of the add wave command to set the show base state (in addition to the documented -showbase option). To disable it add -radixshowbase 0 to the command. Such things are discoverable by configuring a wave window, saving it (File/Save Format) to a file and then taking a look.


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Quartus is for FPGA technology. AFAIK, UVM stuff is mainly used for ASIC-based designs. I will be surprised to see UVM being used for FPGA designs. BTW, you look right in your approach to learn Verilog first then SystemVerilog and UVM later. Modelsim is the third-party simulator supported by Intel's Quartus for waveform simulations. That doesn't imply that ...


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I would have just commented on @bFig8's answer (But I haven't got enough credits). So, since we dragged the variables as shown in above answer, they are shown as -No Data-. To get these new wave information, we'll restart the simulation! This can be done from the ModelSim interface itself. Read this, to find out how to restart the simulation: https://www....


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When I run your simulation, I measure the period of the clock as 2.6ns, not 2.5ns. You need to use a smaller time precision value. Change: `timescale 1ns/100ps to: `timescale 1ns/10ps With 100ps precision, the simulator rounds your #1.25 delay to #1.3. Since you really have 2.6 instead of 2.5, you get a large discrepancy because the multiplier in your ...


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