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# Tag Info

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Soft cores are standard logic modules, written in Verilog or VHDL. They are called 'soft' because they are implemented in the re-programmable logic of the FPGA. You can edit and modify a soft module to tailor it to your needs. If you decide to change the module later, you can just re-program it, and the gates will be re-arranged according to your changes. ...

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Each input requires its own process. Create two "toggle" FFs, and then XOR their outputs together. Toggle the "set" FF when the output is zero, and toggle the "reset" FF when the output is one. module dual_edge_ff ( input set, input reset, output q ); reg set_ff; reg reset_ff; assign q = set_ff ^ reset_ff; always @(negedge set) if (!q) set_ff ...

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Use the solution given in verilog code with two falling edges, followed by another DFF. Adjust the edge directions as needed. Putting it all together, you get: module saw_falling_edge ( input s1, input clock, output reg out ); reg set_ff; reg reset_ff; wire q = set_ff ^ reset_ff; always @(negedge s1) if (!q) set_ff <= !set_ff; always @(...

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That's easy — put the multiplexer outside the module: assign inp = sel ? inp2 : inp1; moduleex s1 (inp, out); You can even do it all in one line if you're so inclined, but this tends to be less readable: moduleex s1 (sel ? inp2 : inp1, out);

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Here's a link in more general terms in which this question has already been answered Kit vs Device: No one on this forum can really give you legal advice, but from what I've read and my current understanding, if your device is sold as a kit, it does not have to be FCC certified. The FCC also has listed differences between intentional emitters and non-...

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You shouldn't need to include the file at all. Instead, simply ensure all files are in your project ready to be compiled by your EDA tool. Most (all?) EDA tools will happily compile Verilog without header files. By the looks of it, you have both files being compiled by the EDA tool. First it elaborates EightBitAdder.v. You have a include statement that ...

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The problem is a ground loop, or possibvly a short-circuit caused by the common connection of the audio signal To fix it use an audio isolating transformer to carry the music signal between the MP3 player and the amplifier board

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It is clear that the only connection to the left side of "R050" is via the plating in the large hole in the corner of the board. Therefore, this hole should not be used for mechanical support at all. Screw threads could easily damage the plating and break the circuit. Furthermore, different mounting holes are connected to different circuit nodes, so all ...

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One side of the resistor is connected to the mounting pad. Bridging the gap electrically would not be a problem as they are already connected electrically. Bridging to the pin above the mounting hole may be a problem as the pin is not connected to the resistor on this side of the board. Mechanically though this will eventually become a problem, cracking ...

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You can use the ternary operator: wire out_s1; wire out_s2; wire out; moduleex s1( .in(inp1), .out(out_s1)); moduleex s2( .in(inp2), .out(out_s2)); assign out = (sel == 0) ? out_s1 : out_s2; The last line means IF sel IS 0 THEN use out_s1 ELSE use out_s2.

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You don't want to have two different always blocks controlling one signal. Here's my version to avoid that always @(negedge s1 or posedge clk) begin if(clk) saw_a_falling_edge <= 1'b0; else saw_a_falling_edge <= 1'b1; end always @(posedge clk) begin out <= saw_a_falling_edge; end This is inferring a DFF with ...

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your first always block is a sequential circuit so, never forget to use non-blocking assignment. your second always block is a combinational circuit and you must declare all the input signals in the sensitivity list. or you can set always @(*) (Line 16,18,21 changed) module SeqDect(rst,clk,ip,op); /*io and internal wires*/ always @(posedge ...

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At the falling edge of clk, out is reset to 0. At the falling edge of R3, out is set to 1. How can I implement this logic in verilog? First, you should consider whether your logic is realizable in the technology you're using. Since you are using Quartus, I'll assume you're targeting an FPGA or CPLD technology. And the logic you're asking for is not a well ...

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In general, when you need "multiplexer", think "case statement". You already have a case statement — so do your output assignment there, too. You'll need to create a separate bus for the output of each of your IP cores — result_add, result_mult, etc.

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Yes, you are correct. Resistance goes low and that is not good for your devices, as the maximal current going through pull-down transistors will increase for several times. But it also depends on your wiring configuration, wires length and protocol bitrate. Typically you can have several pull-up resistors closer to the I2C devices. Please reed this ...

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If all of your modules have pullup resistors then the effective pullup resistance will be the equivalent parallel value of those resistors. This value may be too low to allow your devices to work together. If you want a more specific answer then you need to provide links to the actual manufacturer's datasheets (not the ebay vendor page) for all of the ...

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