# Tag Info

9

C1 is the capacitor that is used along with R1 to set the pulse length using the formula you gave. So you can substitute R1 for R, and C1 for C in the formula. The CONTROL lead is used to adjust the interior comparator levels, in this case it is not used. The capacitor C2 just provides some noise immunity to prevent false triggering. It is typically 10 ...

7

You are asking for a edge to glitch converter, which is usually a flag indicating a kludge. Are you really sure your SoC can't be configured to interrupt on either edge? This is a common feature of many microcontrollers. In PICs it's called interrupt on change, for example, and just about every PIC has a few inputs that are capable of it. If your ...

5

It's an edge detector. 'out' pulses logic high when the switch is opened or closed. The pulse period is determined by C1, R2 and R3. R1 pulls the upper XOR gate input logic low when the switch is open. D1 blocks the C1 voltage from reaching R1 at that time. For a practical circuit, the resistor values are very high. The input leakage values of the logic ...

5

Just add another component: Pick any monostable multivibrator that can generate a pulse with the desired timing characteristics; pick any (slow) two-channel DAC to generate the two desired, constant output voltages (if one output voltage is always GND, you need only one channel); use an analog multiplexer (random example: TS12A12511) to switch the output ...

4

Something like this will work. Timing and bypass components and load omitted for clarity. simulate this circuit – Schematic created using CircuitLab When the output goes high, it turns on Q1 through R1, which turns on Q2 via R2. R2 should be low enough that Q2 stays reliably saturated with the highest load on the 555, plus the 555 supply current. R3 ...

4

Connect the switch to the reset input of the 555, and connect the trigger through a small RC delay: simulate this circuit – Schematic created using CircuitLab The 555 is held in reset as long as the switch isn't pushed. When the switch is held in, the 555 goes through its normal timing cycle once, but it aborts if the switch is released early.

4

This is a perfect use case for a microcontroller, DAC, and a voltage controlled amplifier. With minimal load, an AB audio amp and SPI or on-die dac I estimate your system will hit the 1 us single shot requirement with appropriate firmware on an 8 bit MCU.

3

This XOR gate and delay circuit might work for you: - I'd use a gate with a schmitt trigger input for reliability. Or maybe a couple of inverters instead of the RC: - Inverting the output is basically easy.

3

Figure 1. D flip-flop table with the only two conditions of interest highlighted. Since the D input is permanently high there are only two conditions of interest. CL going high will set Q. R going high will reset Q. R and C in your sample circuit will have a time constant given by $$\tau = RC = 1M \times 0.1 \mu = 0.1~s$$ On each rising edge of CL, Q ...

3

The problem you have here is very similar to one that an oscilloscope designer has to deal with - you need to interface a high voltage to a low voltage circuit while minimizing the load to the source and also maintaining the frequency response so that short pulses are not distorted. To do this the input attenuator uses a compensated attenuator. It consists ...

3

Here is what I ended up using in one of my toy projects due to shortage of components (didn't have fancier switches): The switch S1 controls whether the timer is running in astable or monostable mode. In astable mode (when S1 is open) R1, R2, and C1 control the time constants of the timer as usual. In monostable mode (when S1 is closed) the time constant is ...

3

D1 may not be necessary; may already be present in internal circuit of AND gate. simulate this circuit – Schematic created using CircuitLab

3

The solution to this circuit design request should be pretty easy. Use a half of a dual non-retriggerable monostable multivibrator such as the Fairchild 74VHC221A. Connect it up like this: The circuit will use the two states highlighted in the truth table.

3

Im having trouble wrapping my head around what the threshold and control inputs do and so in the above equation im unsure which capacitor value to use, C(1) or C(2)? The THRESHOLD input determines when the output pulse ends by sensing when the voltage on the timing capacitor (C1 re. your drawing) rises to 2/3Vcc. C2 is used for noise reduction, and is ...

3

The term "gated" simply means that their are two inputs, $\small \overline{\text{A}}$ and B, only one of which can be used at a given time -- one input acts as a enable (gate) for the other. If B is held high, then the '123 one-shot is triggered by a falling edge pulse on $\small \overline{\text{A}}$. If $\small \overline{\text{A}}$ is held low, then ...

3

The Schmitt trigger works similar to a comparator, so imagine you have a comparator with a Vref in the non inverting input. When the input voltage falls below that threshold, the output of the comparator saturates high. If the input voltage then goes above the threshold, the output goes low. If you were to put the Vref into the non inverting input, the same ...

3

How to determine the saturation level when an opamp schmitt trigger starts workig? With the "theoretical" circuit you have shown and the input at 0 volts, upon power being applied, there is no real way to determine what the output state will be. The output anomaly will resolve itself when the input signal passes one of the two thresholds. Once this has ...

3

Do as much as possible in the FPGA that you already have: Since there is a 100MHz clock, the period is 10ns. The minimum counter division is 5, which is easy, getting to 50ns. The maximum counter division for your stated 25ms is 2,500,000. $$\text{ceil} \left( \log_2 \frac {25\text{ms}} {10\text{ns}} \right) = 22$$ You need a minimum 22-bit counter in your ...

2

No, C1 does NOT charge "instantly" when the output of the first gate goes high (BTW, where are your reference designators for the gates?). Because it is discharged, both ends of C1 go high when the gate goes high, which drives the input of the second gate high and its output low. Since this output is fed back to the first gate, this insures that the output ...

2

Perhaps this is doable with the evil 666 555 timer, but we're not in the Pleistocene anymore. A analog implementation will also have problems with button bounce, unless of course you add another klunky analog chip to debounce the button. The obvious way to do this is with a microcontroller. Even the tiny PIC 10F200 can do this. It will use fewer parts, ...

2

I believe it needs adjustments to work properly. For one, the LM393 comparator has an "open-drain" output. It's not the same as most logic gates or opamps. Open collector means that when the + pin is at a higher potential than the - pin, the output is high impedance, AKA: open. It is essentially disconnected from the rest of the circuit. When the - pin ...

2

What you need is a capacitor to store the energy and some kind of regulator to adjust the voltage. Depending on your source a diode on the input to prevent the energy to flow back. For the regulator you can choose an linear one, if you want to have it simple and cheap and if you don't mind to loose a big part of the energy provided by the pulse. If your ...

2

added: Get the datasheet for the 74HC/HCT221 dual Non-retiggerable One shot HC is std CMOS while HCT is TTL input thresholds of 1.3V for 3V logic as well as 5V logic Non retriggerable one shots just loopback to disable the input while the output is active. In the old days we used LS123's to do this, or counters or uC firmware. I guess now you could use a ...

2

Just add 2 more resistors (R2,R3), a diode and a capacitor (C2) R2 and C2 form a simple edge detector circuit. The time constant (C2R2) must be less than the time constant for the monostable (RC). R3 is a pull up resistor which keeps the voltage at the switch high (Vcc). R2 also pulls up the trigger input high (Vcc) so under normal circumstances the ...

2

Among experienced EEs it is a well known fact that electrolytic capacitors (like that 100 uF one) can have huge tolerances. These capacitors often have a 20 to 30 % higher value than their nominal value. As there caps are mostly used for supply decoupling that is usually irrelevant. You are trying to make a (somewhat) precise timer with a timing of a few ...

2

A better drawing of the same circuit can be found here. Where there is also an explanation. In your circuit one of the inputs of U2 is connected to Vcc but that makes no difference to the behavior of the NAND gate. Make the truth table for a NAND and you'll notice that in both cases U2 acts as an inverter. When the button is pressed, the output of U1 will ...

2

The 25mA is what you can run the 123 at without damage. That doesn't mean the output voltage will not be reduced. If you check the HC family characteristics you will find this graph; It shows the output will be reduced 0.3-0.9V at 10mA and 25C. You should increase the 320 Ohm resistor as much as you can and still have the isolator work. If that will not ...

2

For the sake of theory, we assume an initial state of output. Here in your circuit for inverting schmitt trigger, it is assumed to be $+V_{sat}*R_2/(R_1+R_2)$ at the non-inverting terminal, at t= 0, and the circuit waveforms are analysed. Even if you assume it to be $-V_{sat}*R_2/(R_1+R_2)$ at t =0, you will eventually end up in the same waveform, as the ...

2

the Flyback Diode is shown backward from the way I have it in reality ... which makes it a shunt. No wonder you keep blowing a transistor, you basically short-circuit it to 12V.

2

Without the switch pressed, the TR input is open, hence undefined. With an undefined input, you can't expect any specific behaviour. Maybe you intended R1 to be a pull-up? As drawn, it has no function. What voltage do you expect on pin 6 when you apply power? As drawn, it is undefined. A diode could be added to discharge C1 to the power rail. And as ...

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