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14

Many MOSFETs are characterized to allow overvoltage and the subsequent breakdown of drain to source provided the energy limits in avalanche are not exceeded. Provided you don't exceed these limits the device will not be damaged and will perform to the manufacturer's specification. For example, this is a section of an IRFP254PBF power FET datasheet. Both ...


12

The threshold Voltage of IRF3205 is between 2V-4V and the Raspberry Pi gives signal of 3.3v that will be fine No. Gate threshold is where the MOSFET barely starts conducting. So if it varies between 2-4V and you are applying 3.3V you are at best barely turning it on and at worst you aren't turning it on at all. You use at least the Vgs listed to get the ...


6

NMOS devices require a positive Vgs to turn on - that means the gate voltage must be higher than the source voltage. In your circuit you are driving the gate with a 0-3.3V signal, which means the source voltage, and hence output voltage, can never be more than 3.3V (less the threshold voltage to have any significant current flow), otherwise the MOSFET turns ...


4

When The Drain and Gate of a MOSFET are connected together, A two-terminal device known as a ''diode-connected transistor'' results. if drain and gate is shorted then MOS will behave as a diode connected load and it will never go to triode region and can be used as resistive load offering a resistance equal to 1/gm. if drain and source is shorted then MOS ...


4

You are driving your FETs (both of them!) improperly. The \$\mathrm{V_{GS}}\$ must meet or exceed the amount specified for the FET's rated \$\mathrm{R_{DSON}}\$. Note that it's your responsibility to make sure that \$\mathrm{V_{GS}}\$ does not exceed its rated maximum in either direction. For the NMOS case, drive \$\mathrm{V_{GS}}\$ from \$0\mathrm V\$ to \$...


3

The high-side NMOS gate requires a control voltage that's higher than the drain by at least one gate-source threshold. With only a 3.3V gate-source voltage (Vgs) driving it your FET will never turn on fully: the switching node will go only as high as 3.3V - FET threshold. This will limit the output to about 2V, where you should be getting about 6V. Worse ...


2

it turns out the BMS ...delivers 6V during BMS cutoff... They even called the 6V "fake volts", whatever that means. The voltage may be caused by leakage through some device, most likely a transistor. They call it "fake" because it has a very high impedance source. It may be picked up by an oscilloscope, or a high impedance voltmeter, or ...


2

In the 1st video the gate got V2=+24V pulses. The mosfet was working as cathode follower. The pulse output to the coil was V2 minus gate treshold voltage. That means +21V pulses to the joint of the diode and coil. When the mosfet was ON there were massive 3V voltage drop as Vds. That would cause unacceptable losses when compared to what's generally possible ...


2

You got wrong the inrush current. If you do current control, there is no higher current to the motor on startup, only what you intend to drive, usually a result of friction and acceleration. Current limiting is largely based on the same current sensing and control circuitry and algorithm. Except you can add fast protection for a real hard failure- to disable ...


2

It depends on what's connected to J5 and J12. Without knowing the details, I would say you'll likely have problems with J5 in this configuration when the FET is OFF. Think about voltages with the FET off: J5, pin 1 would be +5V and J5, pin 2 would be ~12V (through J12), and you'd have a -7V reverse voltage on the connected J5 device. If the J5 device can ...


2

Other suggestions are correct but for immediate improvement find a “logic level” fet that can operate with 3.3V gate drive. They’re not the best but they exist. Change the 1k to <100 ohms and the 10K to 100K or remove it (the divider shown is slowing down the gate drive and dropping the gate drive voltage even further).


2

You cannot use 1kR resistor on the gate!! I mean, you can, but then the MOSFET turns on and off slowly, therefore having non-zero power for a longer time in the cycle. And heats up... Use voltage of 5-10V and smaller resistor. Or lower frequency.


2

The body diode of the PMOS is used as a reverse polarity protection, if I'm seeing it correctly. Even if the PMOS is off, the current can flow through the body diode because, as can be seen from the placement, it's forward biased when the input is applied properly. By the way, since a PMOS has very high input impedance, it can turn on accidentally. If you ...


1

Imagine a small capacitor between the gate and source of the P-MOSFET. It is the charge on this capacitor (which is also a measure of its voltage) which determines the operation of the transistor. You know that with a discharge path a charged capacitor can retain its charge for a long time. The charge can also leak away through the capacitor itself. To see ...


1

You seem be be between a rock and a hard place: RPI GPIO swing is only between 0 and +3.3V IRF540 wants +5V to fully turn on. You might ask, "What is an acceptable voltage (above 0V) to keep the IRF540 off?". The answer is perhaps a few volts. So a kludge circuit would use a LED to translate the RPI GPIO ranging from (0 to +3.3V) up to (+1.8 to +...


1

Addition to the answer of @Gil, the diode-connected transistor device also stabilizes the voltage gain as follows:- You can visualize a diode - connected transistor as this where M1 is the original transistor and M2 is the diode Now, IN SMALL SIGNAL MODEL: The voltage gain calculation: As we can see the voltage gain depends just on geometrical parameters (...


1

Your PMOSFET probably has a body diode between the drain and source. It's not so important that |Vgs| > |Vgd|, but that Vs > Vd. Otherwise, if Vs-Vd gets too negative, the body diode will happily conduct until fried.


1

Theoretically it should be possible to achieve high efficiency with the right parts. I reproduced your design in LTspice using 'real' components. The calculated efficiency was 81.2%. Here's the circuit:- I chose an STP11NM80 simply because it was the highest voltage NMOSFET in LTspice's database. However this FET has much lower RDSON and total Gate charge ...


1

Another viewpoint. Does your uController's output pin have a pull-down capability and are you using it? If not the Mosfet's gate capacitance (that holds it on) may not be bled away and the Drain to Source connection remains intact. You may try placing a high value resistor (10K or more) from the gate to ground to force the Mosfet gate capacitance to drain ...


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