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14 votes
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"Path to ground with no resistance!" error when trying to simulate a circuit

Your 0V and +5V sources are directly attached to each other at the NPN's emitter. Falstad shows the error as a "path to ground" because one of the sources was 0V. If you had two sources with ...
Polynomial's user avatar
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12 votes

Should I glue BGA chips in the corners before soldering them with hot air?

To add on to the other excellent answers, and to answer your third question: the red glue you see is likely to be some kind of corner staking or underfilling. After soldering, an adhesive compound is ...
Matt S's user avatar
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11 votes
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TTL NAND gate (totem pole) current and voltage analysis

Let me draw out the schematic using the editor (you should have done this, too.) simulate this circuit – Schematic created using CircuitLab One of the first things to understand is the ...
jonk's user avatar
  • 77.8k
11 votes

Is the NAND logic gate perfectly symmetrical?

Depends on the environment. Maybe in your circuit above and in an FPGA they are the same but in an ASIC library you find differences between the various inputs.
Oldfart's user avatar
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10 votes
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Is the NAND logic gate perfectly symmetrical?

There will be a very small difference in that circuit because of the differences in VGS in the N stack while the circuit is sinking current during switching. M1 will be marginally slower than M2 under ...
RoyC's user avatar
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9 votes
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Boolean Logic - Realization with using only 4 NAND gates

Unless I have made an error (very likely) I believe this can be done with 3 NAND gates. The truth table must look like this: $$\begin{smallmatrix}\begin{array}{rrr|cc} U & S1 & L & P1 &...
Carl's user avatar
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8 votes
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Flash memory: What are blocks and pages from a physical standpoint?

Disclaimer: in the following I will (mis)use the term "memory cell" as a synonym for a floating gate transistor. This is not always true, as, for instance, some recent flash chips use a ...
next-hack's user avatar
  • 5,357
8 votes

Should I glue BGA chips in the corners before soldering them with hot air?

What you see around the corners is most probably not glue, and certainly not put there to hold the chip in place during automated assembly. Some SMD components need to be glued down after the ...
Vladimir Cravero's user avatar
7 votes
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Why can't NAND flash memory be a random access memory?

NAND flash does not store data error free. It has a (comparatively) high bit error rate. For this reason, pages of data in NAND are stored with redundant data that allows for error checking and ...
user57037's user avatar
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7 votes

How to build a 3-input NAND gate from 2-input NAND gates or a 3-input NOR gate from 2-input NOR gate?

An alternate approach is given. simulate this circuit – Schematic created using CircuitLab The schematic represents the function: $$Y = \overline{ABC} = \overline{\overline{\overline{AB}} C}$$
nidhin's user avatar
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7 votes
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Identifying this logic gate

The box isn't a box, it shows that the signal goes to both inputs of the 2-input NAND gate. The fact that the line is slightly thicker (as thick as the lines used for drawing the NAND symbols) shows ...
Bimpelrekkie's user avatar
  • 80.8k
7 votes

"Path to ground with no resistance!" error when trying to simulate a circuit

See the words I put in the cropped image below: -
Andy aka's user avatar
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6 votes
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Minimum number of NAND gates required to realize EXOR function

The 4-gate implementation of the XOR function requires the output of one of the gates to be used twice. As far as I know, there's no direct algorithmic way to come up with such solutions; they must be ...
Dave Tweed's user avatar
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6 votes
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Why is this NAND gate not turning on with both inputs off?

The switch is passing the 1 signal through when it is pressed, but when it is not pressed, it's not passing a 0 through - it's passing nothing through. A blue wire in Logisim indicates a wire with ...
user253751's user avatar
  • 12.4k
5 votes

How to build a 3-input NAND gate from 2-input NAND gates or a 3-input NOR gate from 2-input NOR gate?

As equations. \$\overline{ABC} = \overline{(AB)C} = \overline{\overline{\bar A+\bar B}\cdot C}\$
Ignacio Vazquez-Abrams's user avatar
5 votes
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Purpose of resistors in a NAND gate

Since you are interested in attempting an adder with RTL (resistor-transistor logic), let me help you avoid some trouble and offer a designed gate for you: simulate this circuit – Schematic ...
jonk's user avatar
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5 votes
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Negative pluse generator does not reach 0V

You are asking too much of an old, slow, wimpy part. The CD4011 has a propagation time of 60ns, an output impedance of around 1k\$\Omega\$ if you're powering it from 5V (I inferred this number by ...
TimWescott's user avatar
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5 votes
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Is there an intuitive reason for why NAND gate is a universal gate?

Now I know the maths and logic to figure out that every boolean function can be expressed using only AND and OR gates Untrue. You also need inverters. every boolean function can be expressed ...
Chris Stratton's user avatar
5 votes

Minimizing logic expression for two-input NAND gate implementation

Nice question. I'll write up an approach that I use. It's visual. I'll lead towards a solution for (B) that I like to use for cases like this. But I don't have time to work out the complete solution, ...
jonk's user avatar
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4 votes
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How to make a NAND Gate?

Your circuit is a strange mix of upside-down-ness. Figure 1 shows a more-likely-to-work configuration. simulate this circuit – Schematic created using CircuitLab Figure 1. The standard ...
Transistor's user avatar
  • 175k
4 votes

How do registers work in a CPU?

To answer your question of how registers actually work in a CPU, it depends on the CPU. I've reverse-engineered several old microprocessors and they use a variety of register circuits. The Z-80's ...
Ken Shirriff's user avatar
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4 votes
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NAND with LED not working

The problem with your circuit is that the Base-Emitter junction of a bipolar transistor acts like a diode, so when switch A is off and switch B is on you effectively have this:- simulate this circuit ...
Bruce Abbott's user avatar
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4 votes
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CD74HCT03E NAND Gate dont work

74HCT03 is open drain output. That means it can only pull the output low. Try it this way.. simulate this circuit – Schematic created using CircuitLab
Trevor_G's user avatar
  • 46.6k
4 votes

How would I draw A'B' + B'D + A'CD using only NAND Gates?

Any logical expression can be implemented as either using NAND only circuit or NOR only circuit. This is because one can make the basic gates (AND, OR and NOT) using only NAND and only NOR gates. So ...
nidhin's user avatar
  • 8,277
4 votes

Minimum number of NAND gates to implement f(x,y,z,w)=x(y+zw)+yz'

I suggest that you sketch out your proposed solution, just replacing the AND, OR, and NOT gates with NANDs as necessary. Now, look for places where you have two NANDs in series where both NANDs are ...
Elliot Alderson's user avatar
4 votes

SR Flip Flop Latches

It depends on which one fits the application better. NAND: inputs are active-low for the Q output, "set" has priority over "reset" NOR: inputs are active-high for the Q output, &...
Dave Tweed's user avatar
  • 172k
4 votes

Why is this NAND gate not turning on with both inputs off?

Logisim (original or evolution) doesn't simulate the signal propagation with delay. Anything more complicated than SR latches may not work, as you have seen. It works perfectly when connected to ...
devnull's user avatar
  • 8,507
4 votes

Should I glue BGA chips in the corners before soldering them with hot air?

Personally, I'm intimidated by the whole idea of BGA rework with hobby grade equipment, and really wouldn't do it. But, no, if I were doing it, I would be very hesitant to glue the chip in place. ...
Scott Seidman's user avatar
3 votes
Accepted

Monostable out of NAND gates

A better drawing of the same circuit can be found here. Where there is also an explanation. In your circuit one of the inputs of U2 is connected to Vcc but that makes no difference to the behavior ...
Bimpelrekkie's user avatar
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3 votes
Accepted

How is NAND flash going to die when overheating

A few things I can think of. Chance for memory to be erased (poor data retention). In flash memory, charge stored in the insulating gate of a MOSFET acts as the memory element. Under high ...
jbord39's user avatar
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