33

The main driver is the fact that SRAM is highly compatible with the same physical process that is used to implement the actual logic. Indeed, most FPGAs these days are based on LUTs (lookup tables), which are really just tiny bits of RAM themselves. On the other hand, the process required to build EEPROM (nonvolatile memory) requires extra steps — to ...


25

In both cases (EEPROM/flash and DRAM) a small (femtofarads) capacitor is used. The difference is the way the capacitor is connected. In the case of DRAM it is connected to the source or drain of a MOSFET. There is a tiny bit of leakage through the transistor channel and the charge will leak off in a relatively short period of time (seconds or minutes at ...


25

Memory addresses are binary numbers. The range of an N-bit (unsigned) binary number is 0 to 2N-1, a total of 2N different values. Since addresses are passed to memory chips as binary numbers, it makes sense to build them in capacities of powers of 2. That way, none of the address space is wasted, and it's easy to combine multiple chips/modules to build ...


21

In addition to Dave Tweed's answer regarding the fabrication processes involved, most flash-based FPGAs actually still use SRAM to drive their fabric. The bitstream is loaded into the SRAM from flash just like in a more conventional FPGA, the only difference is that the flash is internal. This architecture is evident when you look at their datasheets and ...


21

Three non-volatile memory types match your needs, in order of available size: Wear leveled EEPROM/FLASH. Battery backup SRAM. FRAM. In terms of cost, FRAM is best. All you need is inside the chip, including backup capacitors to complete writing. However available sizes are low. Battery backup SRAM is large and costly in materials. Wear leveled EEPROM ...


21

Here is what I did on a product that's still in mass production. Keep all the parameters and counters in RAM Hook up an interrupt line to a power supply voltage threshold detector When the interrupt triggers, shut off everything that consumes power (most peripherals, LEDs, etc) and back up all the RAM to flash. Turns out there was about 10-20ms of time ...


21

Although they both involve changing the contents of memory, writing and programming are not the same thing. Writing is done with the chip connected to the processor, during a normal processor cycle, and using normal voltages. Programming involves conditions that are not normally produced by a processor. There may be a need to erase the memory first (...


20

I am going to discuss flash memory programming, but a lot of material will be similar to EEPROMs (Electrically Erasable Programmable ROM), since flash memory was derived from EEPROMs in the mid 1980's. As described below, from a physical standpoint, the default state is 1's. But more importantly, I'm going to explain why there is a default state -- you can'...


18

Mask ROM. In Mask ROM, there is no reprogramming. Conceptually, 1's are directly connected to VCC and 0's are directly connected to ground with metalized areas in the construction of the IC. But you literally need to alter the design of the chip and make new chips to change it. So if you commit executable code to mask ROM and then find a bug, you have to ...


17

I feel that the confusion comes from the fact that a clearly writable memory is called read-only in its name. The resolution of the paradox: these memories contain data, which is not or just rarely intended to be changed, and they operate as ROMs for most of the time. Changing the data in them often require special conditions (UV light, high voltage) and ...


15

No, there is no way to know how many times they have been programmed. A typical user will only program them a few times, so you should be OK. If you plan on programming them tens of thousands of times, you should get new parts. EEPROMs from the factory are normally unprogrammed (all 1's). 100,000 writes is a "guarantee", they won't magically die at ...


14

TL;DR: Any sort of a relay computer with integrated stored program memory (not paper tape) is a small-scale production run no matter how much one wishes it to be just a "one off" experiment. When a circuit, even a simple one, is copied hundreds of times, it needs to be engineered to not only be reliable enough that you won't be tweaking/fixing it ...


13

A 1024 x 1 memory chip requires 10 address lines and you get full utilisation of all addresses. Now, if someone brought out a 600 x 1 memory chip, it would still need 10 address lines. It can’t use 9 because that could only uniquely define 512 memory positions. Then think of what would happen if someone wanted to use two of the 600 x 1 memory chips to give ...


13

This has to do with the history of this technology: ROM (contents set in manufacturing), PROM (one time programmable), EPROM (erasable using UV light) and then EEPROM (electronically erasable) that can be written, erased, re-written by the host IC using a serial or parallel interface. For instance, I've used EEPROM ICs that communicate over I2C in order to ...


12

Many USB peripherals include flash-based microcontrollers. Although mask-ROM-based microcontrollers are cheaper, use of a flash-based microcontroller may enable a manufacturer to have one board which can go in a variety of OEM products, each of which reports the name under which it is sold. Some peripherals include firmware that allows them to be ...


12

Put a register in the feedback path and yes. Common in the early 80s when TTL PROMs were cheaper than PALs (before FPGAs came along) Use a clocked register rather than a latch, to hold the ROM output. This register holds the state which forms part of the next ROM address (and may hold outputs too). Then inputs form a further part of the ROM address, so the ...


11

An FPGA (with some exceptions, which don't include the Cyclone family) does not have non-volatile storage, so it will lose its configuration when power is removed. However, it can be programmed (by pull-up/down connections on its pin) to automatically reload a configuration data from another device on the PCB as soon as it's powered up. You will need to ...


11

EEPROM is very expensive in terms of cell size (leading to a larger die and hence higher cost). Manufacturers started trying to get rid of EEPROM as soon as the first Flash based controllers were released. Especially when you consider the varying user requirements for the amount of EEPROM, it makes more sense to emulate in Flash, despite the limitations. As ...


10

Originally, the devices called "ROMs" were in fact read-only. The data stored in them was put in place as part of the manufacturing process and could not be changed. When the first UV erasable memories were introduced they were named EPROMs, but they were not truly read-only. By a relatively long exposure the memory could be erased, and then could ...


9

USB keyboards can be used to do interesting things on a PC/Mac. And you could combine an USB keyboard with a mouse into one HID, using a microcontroller for example. Cheap USB mice should still use ASICs that are not reprogrammable IMHO, because masked ROM costs less than flash.


8

There is no limit to the amount of read cycles you can do, but repetitively reading causes something called read disturb. Essentially, reading lots from the same segment without an erase cycle can cause the data to be read incorrectly, and also corrupt surrounding cells in specialised cases. More info here http://en.wikipedia.org/wiki/Flash_memory#...


8

More than anything, it depends on your requirements. While Size, Weight and Power (SWaP) are the main drivers for ICs in-general, if you aren't compelled to develop an ASIC because of those requirements, Performance is your next consideration, which may push you back to an ASIC anyway, but, you may be able to use an FPGA if you can afford the SWaP trade-...


8

Originally, writing to an EPROM was done with special equipment - an EPROM Programmer - these parts could not be programmed in-circuit, as they required higher than normal voltages and special writing routines. Newer EPROMs can be written in-circuit, but require special commands which take more time than a write to RAM - a simple "write to memory" ...


7

Yes, you understand the definition of volatile and non-volatile memory. From that alone you'd think non-volatile is always better. However, in the real world that is not true since the different technologies for making these memories cause other attributes to appear beyond volatileness. Tradeoffs that various different memory technologies force on us ...


7

From what i know there are two options: Use flash (emulated as EEPROM for ease of use) according to this Appnote Use the backup registers (20 byte of battery backed registers) according to the Reference Manual Pages 67 And 79 By The Way if the you move one of the bigger brothers (F2-F4) of this chip you get a whole part of ram battery backed something like ...


7

EEPROMs are slow to write (milliseconds) and they wear out after a certain number of writes (reads are generally unlimited, with exceptions). You can wear an EEPROM out in a very short time if you're writing to particular locations continuously. For example, this 1Mbit 24C1024 has a write time that can be as long as 5ms and a 'typical' life of 10^6 cycles. ...


7

The optimistic estimation would be based on the assumption that your system accumulates data until it can fill one complete erase block, then writes all the data in one go. In that case, your eMMC will live 4'000'000 * 3'000 / (4*20) = 150'000'000 seconds That's about 4.75 years. However, if for example your system writes each 4K block separately, the ...


7

NAND flash does not store data error free. It has a (comparatively) high bit error rate. For this reason, pages of data in NAND are stored with redundant data that allows for error checking and correction. This means that when you read a byte from NAND flash, it may have an error. In order to check it or correct it, you need to read the whole page of data to ...


6

It's by definition. A flash memory that allows writing individual bits is called EEPROM. Flash differs from EEPROM in that erasures are done in blocks, rather than individual bits. Because erasing is a relatively slow operation, and must be done before writing, performing the erase in a large block makes large write operations faster, by virtue of erasing a ...


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