# Tag Info

8

The simple and obvious answer that meets your specs is: This thresholds the input around the midpoint of what you say the high and low levels are. In practise a little hysteresis is probably wise: This will create about a 50 mV hystersis band. For example, when the input goes high so that the output goes high, the input has to go 50 mV lower before the ...

7

You could have a slot just wider than the tubing around an inch long just under the port and extending outwards. Something like this:

7

You're using the PNP as an emitter follower so no wonder it adds a voltage to the bottom side of the waveform. What you need to do is use an NPN or an NMOS transistor. Then the polarity of the signal from opamp U1 (used as a comparator) is "upside down" but that is easy to fix: just swap the + and - inputs of the opamp. In the case that you use an NPN, do ...

6

If nothing is said about it in the data sheet and application notes (as does occur sometimes), leave them floating. If there is direction in the data sheet or application notes, follow it precisely, as @IC_designer_Rimpelbekkie says. I can't recall any exceptions, but that doesn't mean that there are not one or two types of op-amps somewhere that require ...

6

Offset voltage is unavoidable error in the construction of a opamp. Nobody "places" it anywhere. Manufacturers go to great lengths to reduce it, but of course, can not make it zero. It also makes no sense to ask whether the offset voltage appears on the positive or negative input. The offset is between the two inputs. A opamp ideally does:   ...

6

You can use an opamp to perform the translation if you like. But there's an easier way : using 2 resistors you can both attenuate and level shift at the same time. I have chosen values that give a 10:1 attenuation and an 0.5V unused range at each end of the scale - scaling to the correct values is simple in software. simulate this circuit – Schematic ...

6

The analogue outputs from this chip will have a DC voltage of approximately 50% the DC supply voltages so that the output can produce superimposed AC waveforms without unreasonably clipping. This is standard for most electronic audio chips and most signal processing chips. You need to connect to an amplifier using a DC block circuit so that the resulting ...

5

It should be fairly stable for a given chip, when measured at the same temperature, supply voltage and common-mode voltage (and assuming the chip is not damaged by overheating, electrical transients etc.). There will be some drift over time, but it should not be large for most op-amps. Some early CMOS-input op-amps had significant long term drift if they ...

4

First let's remove the fluff. The 20K and 6.8K are there so that if the input becomes disconnected, the output will be approximately zero (because the effective input will be 1.268V, which is fairly close to presumed mid-scale of 1.25V. The gain of this circuit is $1 + \dfrac{27K}{13K || 5.6K} = +7.90$ For the offset, assume the input is mid-scale of 1....

4

To analyse the gain & offset behavior of this circuit we can ignore the 20k and 6k8 resistors on the input, since it seems that their only purpose is to provide a known bias voltage if the input is not connected. So now the circuit looks something like: simulate this circuit – Schematic created using CircuitLab But with a little rearrangement we ...

4

Three options: Mount at Edge - probably the most sensible option is to simply mount the part at the edge of the board. This way the ports overhang the edge of the board and you don't need to worry about height. You could also mount at the edge of a slot in the board for the same effect. SOIC to DIP Adapter - You can get SOIC to DIP adapters (or make one) ...

4

You are trying to get zero out for zero in by dead-reckoning. Any imbalance anywhere will give rise to a DC offset. Although all the components in the two sides are nominally the same, you cannot assume exact matching. You use seperate comparators for the H and L FETs, which will have different offsets and speeds, level translators with different speeds, ...

4

You need resistors to ground on these inputs to keep the input dc bias from just charging up the capacitors. In other words it's bad design and won't work. They may be limiting at 0.7 volts because the model has internal protection diodes in place. See note 2 in the data sheet: - Note 2: The inputs are protected by back-to-back diodes. This means that ...

4

Actually everything is working perfectly. You have just configured the ADC in differential mode so that it measures the difference between PC0 and PC1. This difference can be positive or negative depending on whether PC0 is greater than PC1 or PC1 is greater than PC0. When they are equal to each other, the ADC reading is in the middle, which is what you are ...

3

Forget about the 20k and 6k8 - with a voltage input of 0 to 2.5 volts these resistors do nothing to explain the circuit. Then you are left with the simple case of examining two scenarios; namely the 0V in scenario and the 2.5V in scenario. With 0V in, the inverting input will acquire 0V by virtue that the op-amp has negative feedback. So, what must the op-...

3

Use an op-amp to create a mixer circuit and subtract the 3.07 volts from the signal: - V1 can be your input and apply -3.07 volts DC to V2. If you want to restore the polarity of your signal (because Vout = -(V1+V2)) use an op-amp inverter afterwards. If the dc offset is slightly moving with respect to the signal then something like a data-slicer would ...

3

First of all you should really get better resistors. 5% with a strain gauge is just ridiculous. To "trim and calibrate" your measurement you should just leave your gauges be, i.e. leaving them in a known state, measure the output and save it in a variable in your micro. This value should then be subtracted from all subsequent measurements. If you can you ...

3

Input offset current is an input referred term that develops a voltage across the input resistors, and is usually calculated for a no-input condition (so a static analysis). The input offset current is precisely what it says: the difference in input current between the two inputs. In this case, that difference in input currents will develop a voltage across ...

3

There are several ways to do this, for instance using an opamp to sum 2.5V to your signal: This is an inverting summing amplifier, so for $R1 = R2 = R4$, the output would be $Vo = -(V_{AC}+V_{DC})$ If you want to keep the phase of the signal, a non-inverting summing amplifier would be like this: In this, $R_3,R_4$ control the gain of the amplifier, ...

3

Your bridge connection is most likely rotated by 90 degrees. No bridge would ever have this much offset. If you are sure it is not damaged, first disconnect any circuitry on the output pins and measure again. Then, check the pinouts and make sure they are properly connected. Best bet is to try rotating the strain gauge; that is, apply power to SP and SN ...

3

Andy aka is on the right track, but your circuit is in very bad shape. First, there is no need to establish a virtual ground for the Vcm of the input amp. A simple capacitor to ground will do. Second, although you have accounted for input offset voltages on the LTC6248s, you have not considered input bias currents. With nowhere for that current to go it ...

3

Your are trying to operate your op-amps beyond the rails. The reference leg of your bridge is at, $$V_R = 12 \dfrac{100}{4800} = 250 \text{ mV}$$ The RTD leg of your bridge will span from 250 mV to $$V_{T,max} = 12\dfrac{250}{4950} \simeq 606 \text{ mV}$$ Say for arguments sake, the RTD leg is outputting 300 mV. You now have a differential input ...

2

Mostly, when it comes to full bridge strain gauge circuits we use an instrumentation amplifier with the reference input connected to a DAC output. This is pretty common in industry and allows nulling of offsets via software at any point. Pretty useful for pressure gauge's too.

2

My question is: Are the gain and offset errors in the data-sheet fixed values or are they maximum values and also statistical or indicate a range? As pointed out in the other answer, the actual error varies from device to device, and when the temperature of the device changes, and maybe in response to other effects like if the power supply varies, etc. ...

2

Trivial solution: coupling capacitor on output. This assuming the DC offsets aren't so bad as to cause clipping when the AC signal is overimposed. If you have more sophisticated needs like preserving high CMR (unclear from the question if you do), then read http://www.ti.com/lit/an/sboa003/sboa003.pdf If you have high-level DC bias on the input, then ...

2

The simplest way to eliminate your problem is to reduce the effective impedance of the source, and a voltage follower will do nicely simulate this circuit – Schematic created using CircuitLab The choice of buffer op amp is left to you, depending on the frequency response you need.

2

Slight improvement (less power consumption and fewer parts): simulate this circuit – Schematic created using CircuitLab U1 has to be very low input bias current, of course. You might want to add some series resistors to the non-inverting inputs in case the piezo voltage exceeds 2.5V.

2

They do not list anything on the datasheet about the REF pin, although it clearly lacks the 'overvoltage protection' shown on the (other) input pins. Yes, you should keep it within the supply rails, or at most a few hundred mV beyond the rails. Since you need to drive it with a low impedance it would be best to feed it with a buffer that is also powered by ...

2

1) Yes. The usual way to handle this for an AC signal is to construct the feedback so that it has unity gain at DC, and your required higher gain above your minimum signal frequency. That way, only 1x the input offset voltage gets onto the output, rather than gain times. 2) The problem with bias current is that the resistance of the DC path attached to ...

2

By definition, your bridge is unbalanced. you don't say where the bridge comes from, or what it is, or if all the elements are active, or which ones are simple resistors, but its pretty clear that on one side the resistors have about a 2:1 ratio, and on the other a 1:2 ratio (give or take). Its possible that you've reversed your excitation with your ...

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