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15

Thanks for the pointers, markt and chris-stratton. The semihosting option turned out to be quite straightforward. I managed to find the source for a couple of simple logging routines that can send messages to the OpenOCD console. I'll post them here since (i) they required some modification to work and (ii) I think this info is not super easy to find for ...


6

From the error message it seems that the debugger cannot locate where the Flash begins, so it fails to load the file. In the F4 HAL Eclipse template this Flash origin address is set correctly for an STM32 but because you are using a general Cortex-M project, and so this address is not correct for an STM. This step is described in the article you have ...


6

So I figured out my problem... Naively I believed the JTAG connector (via the st-link v2) was enough to power the board. I'm guessing trying to run the code (and blink the LED) while only powering the board through the JTAG pins could not supply enough current and the board kept resetting (hence the JTAG connection would break). Long story short, ensure ...


6

CMSIS is the generic name for ARM-specified infrastructure around Cortex processors. The project we know today as DAPLink actually started as mbedmicro/CMSIS-DAP, we can find multiple references of the rename in the project history. "CMSIS-DAP" name became ambiguous as it was both the name for the spec and Mbed's implementation. So today, CMSIS-DAP is the ...


5

Indeed the documentation for this amazing feature is rather poor, however there is a guide for ChibiOS. Basically this boils down to: pass -rtos auto to {TARGET_NAME}.cpu configure in the Tcl configuration script use thread commands in gdb, where info threads is the probably the one you will use most


5

The JTAG specification (which is reasonably described on the wikipedia page) defines an IDCODE instruction as part of the mandatory implementation, and a scan chain intended for debug will typically conform to this part of the spec to provide tools with some basic access information. Remember that even for a single chip, there can be multiple TAPs in series, ...


3

There should be no real interaction between GDB or OpenOCD and the virtual serial port of an STM32 Discovery or Nucleo board, however the modemmanager package installed by default in Ubuntu and derived distributions will substantially delay availability of the CDC/ACM device after each reset, which typically includes not just connections but some ...


3

@Arsenal is right. OpenOCD requires a board-specific config file which is in your case is probably for an STM32F4. In Debug Configuration check the Debugger tab of your OpenOCD Debugger and change the config file at the Other options to match your board. You can check the existing/available config files in the following directories: \openocd-0.9.0\tcl\...


3

It's definitely possible. I haven't tried it yet but I did come across a post I found on hackaday that you might find useful. http://spin.atomicobject.com/2013/01/18/stm32f4-discovery-toolchain-mac-os-x/ Good luck!


3

I worked around my problem. Still very interested to learn about those states, though! I botched the connection through port 3333, and used openocd's piping capabilities: .gdbinit # Open openocd and pipe data throudh stdin/stdout. # Openocd quits after gdb exits. target remote | /usr/local/bin/openocd -f linux_config.cfg openocd.cfg: gdb_port pipe And ...


3

I don't believe openOCD even supports the Atmel AVRISP mk2. The list of supported dongles is here. OpenOCD uses the JTAG communication protocol to communicate with, set breakpoints, and control its target processors and FPGA's (IEEE standard 1149.1 in case you care). The Atmel AVRISP mk2 does not communicate using this protocol (in general). In limited cases ...


3

$ telnet localhost 4444 > halt target state: halted target halted due to debug-request, current mod xPSR: 0x81000000 pc: 0x00080107 msp: 0x20000598 > flash write_image blinky/blinky.elf You usually need reset init before a flash erase/write, halt may not be enough. In gdb it is monitor reset init. The flash also needs to be erased before writing: ...


2

You gave a pretty big clue when you said that the LED was in a "neutral" state. There is no "neutral" state for a properly functioning digital output, so you probably meant that the LED is dimly lit. And that usually means that the pin driving the LED is being turned on and off so fast that you can't see the blinking. You didn't show your code so we can't ...


2

The FT2232H uses High Speed USB, and the error translates into "problem in USB communication". I`d recommend trying another USB cable first - but this seems not to be a problem here, as it works in other configurations. You should use the newer ftdi driver in OpenOCD 0.7.0: source [find interface/ftdi/olimex-arm-usb-tiny-h.cfg] You can ignore the warning, ...


2

Short answer: You are using OpenOCD in LE mode when your CPU runs on BE (or vice-versa). You have to specify the correct -endian switch for the target command in your OpenOCD configuration. Longer asnwer: Where is the endianness mismatch? Regardless of endianness, the data is being read from the flash one chip_bus_width bits at a time, in this case ...


2

In the recent STLinkUpgrade 3.3.0 I can see checkbox "Change Type" offering "Debug + Mass storage + VCP" or "Debug + VCP". Seems like the way to go. To download the latest and greatest version: https://www.st.com/en/development-tools/stsw-link007.html Just click on the "Get Software".


2

I wrote a tutorial for setting up the STM32F3DISCOVERY on Mac OS X (tested on 10.8 and 10.9) using the GNU ARM toolchain, Eclipse and OpenOCD: http://www.davidrojas.co.uk/stm32f3discovery-on-mac-os-x-using-eclipse-gcc-arm-and-openocd/ It should work with the STM32F4DISCOVERY too (they are both Cortex-M4, and use the same debugger), just change the line ...


2

The comments suggest you are trying to operate in 'star topology', but as far as I know, that isn't a well defined implementation. Please confirm you're using daisy chained topology, where the multiple TAPs make up a single long shift register. Debug tools ought to cope with this since it sometimes occurs implemented in a single chip. The TAP IDs that you ...


2

DAPLink states that it uses the CMSIS-DAP protocol, which is supported by OpenOCD CMSIS-DAP, as the name suggests, is a protocol and firmware developed by ARM - the company which designes the processor cores. The firmware itself supports both SWD and JTAG. http://www.keil.com/pack/doc/cmsis/DAP/html/index.html?_ga=2.84588765.557139549.1541455299-619225292....


2

When you set a device's IR to BYPASS, it will map a one bit register with no CAPTURE and UPDATE actions to DR. The IR has a fixed length, let's assume two bit: 00 BOUNDARY-SCAN 01 IDCODE 10 PROGRAM 11 BYPASS Further, assume that the PROGRAM chain has 16 bits, then you could program the first device with programming data p by sending (x means the bit is ...


2

Change the IDE to something with better debugger - for example eclipse with set of plugins or use preconfigured IDE like atollic studio. The you can use tracing - to see live changes of the variable or set the stimuling triggers like variable read or write.


2

NRST pin is hardwired directly to VDD so not all ways to reset the MCU core are available.


1

It works only for boards with ST-Link V2. Boards with ST-Link V3 do not have this 'type' option, e.g. NUCLEO-H743ZI (V2) is fine, NUCLEO-H743ZI2 (V3) does not.


1

I accidentally forgot to remove the jumpers to allow upload to the motor controller and I don't know what happened to the board. It does not have blinking leds on the lower half of the board anymore as a result. Which board - discovery or the 'motor controller'? If you are talking about discovery, then there is nothing wrong with it, since you flashed the ...


1

I found a way to fix it. First I launched OpenOCD with some special flags: sudo openocd -f interface/stlink-v2.cfg -f target/stm32f0x.cfg -c init -c "reset halt" All while holding down reset for about half a second. Which causes it to connect in a halted state. Open On-Chip Debugger 0.9.0 (2016-07-31-11:32) Licensed under GNU GPL v2 For bug reports, read ...


1

You can reset the option bytes of a STM32 device to their factory settings with SEGGER's J-Link Unlock STM32 tool. It is included in some SDKs but you can download it here : https://www.segger.com/downloads/jlink You can also use J-Flash that is also included in J-Link to do a full erase. Check this link too, it might help.


1

Hmm, looking at your pinout, TDO: Pin 19 (Model B) -> Pin 21 (RPI2) TDO is Pin 18 or Pin 29, but not pin 19.


1

OpenOCD ships config files for XDS100v2, so it is supported. But you may need a different driver for OpenOCD that would prevent you from using CCS.


1

It's an endian issue. The memory is working fine. It's simply to do with the software reading out 32 bit words and the mapping of the individual chars (single bytes) to their position in the 32 bit word. I was able to predict the output and compare what I predicted to what was actually read. A 32 bit word stores 4 bytes = 4 single ASCII characters. Let's ...


1

After nrf51 mass_erase, you probably need a reset halt. If that doesn't help: If you have issues, add "set WORKAREASIZE 0" before sourcing nrf51.cfg to disable it Did you try that? That should eliminate problems, but the flashing will be slow. You may have better luck with a value greater than 0 but smaller than the default, like "set WORKAREASIZE ...


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