23

As Joshua says, something is clearly wrong here. The synthesis tool has clearly optimized away your memory. Having had a quick readup on the ice40 blockram it seems to have registered output, so making the output combinatorial would force the tool to use a big bunch of registers instead of a blockram. Speculating a bit here, but I wonder if readmemh only ...


18

I actually have some relevant experience on this very subject. Many, many years ago I grabbed a bunch of PS2505 optoisolators which turned out to be PS2506s. No big deal right? It turns out the PS2506s are INCREDIBLY slow compared to the PS2505s. My friend and mentor, Don Shepherd, gave me this sage advice. Choose R1 so that about half of the available ...


14

Normally if my design shows a drop in resources it means that it actually 'optimized' something away; I suspect the same has happened here. Typical FPGA toolchains will cut everything away that does not directly or indirectly influence an output pin. Best way to check what Yosys is doing seems to include using the 'show' command: http://www.clifford.at/...


13

You could try making the loop actually do something. As it stands the compiler is quite rightly saying "This loop is doing nothing - I'll get rid of it". So you could try a construct I use frequently: int i; for (i = 0; i < 10; i++) { asm volatile ("nop"); } Note: not all targets for the gcc compiler use the same inline assembly syntax - you may ...


13

Bit fields don't work like that. Cventu's answer shows a correct way to use them, but in this case, I recommend avoiding them altogether. Instead, create an array of 8-bit values and use shifting and masking to access it: uint8_t flags[16]; //Initialize the flags void init_flags(void) { for (i = 0; i < 16; i++) { flags[i] = 0x00; } }...


13

I think Brian's non-SW answer is the best but here's a purely analogue solution. Use a circuit that inherently chooses the highest voltage input (from several) and puts that to the output. Ditto the circuit for the lowest voltage. Consider the precision rectifier: - It produces an output voltage that follows the input voltage throughout its positive range. ...


11

One window comparator, a 3 bit counter, and an 8:1 analog mux to connect one thermistor to the comparator. If all you need to know is that they are all fine; that's 3 chips, job done. (74HC163, 74HC4051, comparator, plus something like a 555 to clock it). As Andy says, the MUX (e.g. 74HC4051) has fairly low ON resistance, so each thermistor connects to one ...


10

I will leave it to an LRM expert to provide a more detailed answer, but in short, your approach should be valid - I ran a quick test with a recent version of Quartus, and it handles '-' like it's supposed to - the logic generated is reduced as expected when the output is defaulted to '-' ('X' works too, by the way). More on the approaches you listed: Not ...


10

I think it is actually possible to run LTSpice from the command line and have it run a transient simulation: On Windows: cd <wherever LTSpice is installed on your computer> scad3.exe -Run -b MyCircuit.asc On Linux: cd ~/.wine/drive_c/Program Files (x86)/LTC/LTspiceIV wine ./scad3.exe -Run -b MyCircuit.asc


9

There is an actively developed free and open-source Arduino bootloader / firmware called OptiBoot, that might be of interest. From their site: Optiboot is a quarter of the size of the default bootloader, freeing 1.5k of extra space. Many Arduino / clone boards now ship with OptiBoot instead of the classic Arduino firmware, though not necessarily with the ...


9

Since in one comment you state that "each CPU tick is worthy" I suggest using some inline assembly to make your delays loop just as you want. This solution is superior to the various volatile or -O0 because it makes clear what your intent is. unsigned char i = 10; __asm__ volatile ( "loop: subi %0, 0x01\n\t" " brne loop" ...


9

It sounds a bit confusing, but maybe something like this can help: struct bits_field { unsigned char bit_7 :1; unsigned char bit_6 :1; unsigned char bit_5 :1; unsigned char bit_4 :1; unsigned char bit_3 :1; unsigned char ...


8

You can convert from binary to packed BCD without any division using double dabble algorithm. It uses only shift and add 3. For example convert 24310 = 111100112 to binary 0000 0000 0000 11110011 Initialization 0000 0000 0001 11100110 Shift 0000 0000 0011 11001100 Shift 0000 0000 0111 10011000 Shift 0000 0000 1010 10011000 Add 3 to ONES,...


7

If you really only have two devices, this can work if you're careful. Some points to consider: Make sure to switch the slave select line only between full sequences and with some dead time before and after you try to transfer data. Many chips use the leading edge of SS to reset their logic to the start of a new sequence. Even if you are using the same ...


7

Is supercompilation (synthetically combining program elements until an optimal algorithm is found) used when appled to HDL? Not in the sense of the sort of optimizations described in that book. Generally speaking, an HDL synthesizer is free to make any optimizations which do not affect the externally visible behavior of the design. They can make changes ...


6

In short: It's legal VHDL and it's typically supported by synthesis tools. It is however rather uncommon to see it used. I don't really know why. Your code seems to me to be a good example of when it would be meaningful to use it. There is however one drawback that one should be aware of: at synthesis, the functions driving outputs where don't care's are ...


6

The key to maximum speed appears to be Figure 8, the frequency response, plotted at different values of RL (R2 in your circuit), and the fastest is with RL=100 ohms, where full amplitude is maintained up to 1 MHz corresponding to rise and fall times below 0.5 us, correlating reasonably well with Figure 7. Now at the conditions for measuring Fig8, the LED ...


6

Yes you could assume that. If you declare variable i as volatile you tell the compiler not to optimise on i.


6

An idea once I had, but never tried, is to treat an ultrasonic transducer like a high-power crystal oscillator. Your typical crystal oscillator circuit looks like this: simulate this circuit – Schematic created using CircuitLab Simplistically, the crystal (along with the 2 capacitors) provides a 180 degree phase shift at its resonant frequency and ...


5

I cross posted this question on the Xilinx Forum here: http://forums.xilinx.com/t5/Implementation/How-to-determine-what-part-of-the-design-consumes-the-most/td-p/393247 This answer is largely based on the comments there. Thanks to Deepika, Sikta and Gabor. First, enable 'Generate Detailed MAP Report' in the map process properties (-detail). Then, open the ...


5

At least two factors: bigger caches means longer wires, so it takes more time for the information to travel (remember, at 1Ghz, light travel 30cm per cycle, and electrical signals are slower), both from the address to the memory cells, and from the memory cells to the place where the data is used. if your cache is fully associative, that means that you ...


5

Prior to learning to implement this using timers/interrupts I would recommend not rolling your own delayMs function. There is a SysCtlDelay(int count) function described in a similar situation Simple delay functions for TI Launchpad? here. I found an example gist from someone else here https://gist.github.com/ctring/7f12d812fb594eecc493 which shows how to ...


4

LTSpice can be run in batch mode with the -b command line switch. From the LTSpice Help file: -b: Run in batch mode. E.g. "scad3.exe -b deck.cir" will leave the data in file deck.raw How to read and interpret the .raw output is left as an excercise for the reader. Also note, among the command line switches: -ascii: Use ASCII .raw files. Seriously ...


4

Have a bit more trust in your compiler. Write the code in C, compile it and look at the disassembly. Unsure which toolchain you use, but avr-gcc creates pretty well optimized code. lds r24 , lowbyte ; 2 clocks lds r25 , highbyte ; 2 clocks adiw r24 , 0x01 ; 2 clocks - Add Immediate to Word (= 16 bit) sts lowbyte , r24 ; 2 clocks sts ...


4

The floating point is the killer here. It appears to be doubling the amount of code generated, not that number of instructions is necessarily slower. It has to make a number of calls to what I assume is a float to int int to float. Interestingly changing from double float (1.4) to single float (1.4F) didnt change the overall result, although again the ...


4

There are a number of factors that need to be considered here. Analogue circuits can be sensitive to routing things around just to make certain other features work. So the proposal of how to reduce jumpers has a lot to do with just how those jumpers are used. A. If jumpers are used to simply isolate the circuit sections in the case a board is under debug ...


4

The switch statements gets killed because it gets optimized to lugar = (lugar > 0) && (lugar < 7) ? lugar + 1 : 25. If lugar is smaller than 8 and not equal to 0 you always do +1 otherwise it's equal to 25. Your code only needs an if statement. Hence only 2 options remain in the optimized code.


4

As all cases except default are the same code, the compiler is allowed to reduce that to a single case + default. Why not? There is no need to bloat the result code with the same instuctions several times. In fact the code is simple if((lugar>0) && (lugar < 8)){ ++lugar; }else{ lugar = 25; } and that is exactly what the compiler will ...


3

I believe problem is in PROGMEM attribute which saves const array into flash memory. To get values you need a memcpy_P() or so. For direct access try avoiding PROGMEM attribute. pwmtable_10[fade] gets random RAM value. See http://www.nongnu.org/avr-libc/user-manual/pgmspace.html


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