22
The yellowish PCB laminate has better electrical insulation than some solder masks, so sometimes air gaps and solder mask free areas are used to separate the high voltage and low voltage side.
I work as CAM/CAM designer in a PCB fab, and recently we made a run of boards with no solder mask at all, because the boards were going in X-ray machines. Extremely ...
9
Your initial impression is incorrect. Here is what the impedance of various capacitors in the same package looks like.
Source
In order to get a sufficiency flat power supply impedance over a wide bandwidth, one needs to use a selection of different capacitors.
7
Many things go into designing the width of the PCB trace, including temperature rise for current. Others are voltage drop, impedance, PCB fab capability, cost, packing density.
However, temperature rise is rightly one of the 'do not exceed' specifications.
A rule of thumb is just that, something you should follow most of the time. You will always be able ...
7
I am sorry to be the bearer of bad news! There are a few things that stand out. In addition, even after these problems are corrected, there's still going to be a lot of learning and analysis to do. Please don't take my suggestions as criticism; RF is tricky :)
Also, there have been hundreds of books written on RF. I can tell you some things to look for, but ...
6
This might be the drawing for SOT804-4, which you are looking for. The land pattern is on p.3 .
The second row isn't soldered to the board, if I'm reading the drawing correctly.
I'm guessing, each oblique pad in the second row is connected to the pin on the outer row. So, the second row would be signals, not all grounds. If you have the an IC in your ...
6
It's not only the dielectric strength that you must worry about, but also the spacing between connectors. As you know, high voltage tends to arc. Because of this, you won't find connectors that are closely spaced in high voltage parts, even with high dielectric strength materials, per IPC spec, there is a minimun distance even if there is insulation.
If ...
5
So, could I find a distance between both connectors in which the VCC+
connector and VSS- connector will be safe from breakdown?
Yes, but it's already been done for you in the IPC specs the table below shows this. It might be best to use two separate 1 conductor connectors, instead of finding one that has both (although the connector wouldn't be keyed for ...
5
A couple of things.
I assume you mean "DIP" not "PID" for the existing package.
That socket you link to is not for mounting TQFP, it is for PQFP packages, also a very old package.
In my opinion, there isn't a good socket for TQFP packages, any you find will be expensive, have a large footprint and be unreliable - especially if you have much vibration.
If ...
5
There may be some small benefit. Using a Murata's SimSurfing tool, I graphed the impedance vs. frequency curve for a 2.2uF 0402 (1005 metric) MLCC compared to an 0.1uF one in the same package. The 2.2uF cap is shown in blue in and the 0.1uF in green:
As you can see, the point of resonance is higher in frequency with the 0.1uF, as would be expected of a ...
4
We call this a "netlist", but generally don't edit it directly as text
It is possible to represent a circuit as a serialized text representation, versus the graphical schematics we normally use. The traditional name for this is a "netlist", as it is a list of components and the nets (nodes) that connect them together.
While there are a wide variety of ...
4
A common mode choke acts as a low impedance path for normal (wanted) differential currents flowing to and from a load. For these currents, the net magnetic field in the ferrite-core is largely zero. Or, put another way, the ampere-turns for the forward load current is cancelled by the same ampere turns flowing back from the load.
This means that copper ...
4
thermal/vibrations stresses in the environment.
directly contradicts
have the user be able to take the chip out to replace it
Clearly, if you need potting for your components, you don't want your user to be able to take out parts.
You'd normally just do this with a firmware update routine built into the firmware you deploy. For example:
Your firmware ...
3
If you understand creepage is the ionic breakdown of a good insulator due to the accumulation of dust and humidity, then you will understand why an air gap is good. You may need 2 connectors.
Clean air is about 5kV/mm between smooth parallel surfaces. Plastic can be >10kV/mm.
The highest level of indoor contamination of residential humid dust on the ...
3
The pattern is on the copper layer. It appears they have used the "hatched" pour option in the PCB design software with an unusually low fill. You can see the regular pattern of the pour being broken up by tracks and one area where the pattern is missing completely, presumably because the "remove dead copper" option was used when making the pour.
It looks ...
3
LTSPICE schematics save as SPICE netlsts which are text
annother other way to do circuits in text is ASCII art eg:
to get 50% duty cycle the easiest way is the 1 resistor circuit,
----+--- vcc
|
+-[R1]--------|--------+
| ...
3
Page 3 of that document gives you a land pattern. You don't have to guess.
In general, data sheets give you recommended PCB layouts, or refer you to documents (like that one) that give it to you.
3
So I found what the issue was, I made a stupid mistake between the schematic and PCB so make sure you always triple check everything before sending the board out for manufacturing. I miss-connected VDDA to GND and VSSA to VDD in the schematic and only noticed it after designing the PCB and me being stupid I got distracted or whatever and never updated the ...
3
Indeed there is. The most obvious one is cost. Ceramic capacitors of different values in the same FOOTPRINT (not necessarily package since height may vary) do not cost the same.
Beyond that, ceramic capacitors have different impedance curves (due to the different parasitics as you mentioned) and DC bias curves for each combination of capacitance, dielectric,...
2
I'd also take a look at the IPC 2221[edit: Electrical Clearances] standards before going any further with the PCB design. For a high voltage PCB, the one thing that matters the most is the material selected for the core/prepreg. Depending on the availability and budget, you can go with extra overcoats and better alternatives/versions of FR4. Also, consider a ...
2
Use two SMD pads for each pad:
100% roundness for inner corners
0% roundness for outer corners
Overlap the two SMD pads to create a single shape. Your 48-pin package, therefore, gets 96 SMD pads.
Pads need unique names. Name the sharp pad with prefix _. For example, name the pin 1 rounded pad 1 and name the pin 1 sharp pad _1.
The screenshot shows five ...
2
See HELP AUTO for more information on what I'm about to describe. The easiest way to get those traces routed, would be to type the following into the command line:
AUTO U1_S* U2_S* U3_S*
Followed by the Enter key. The asterisk is a wildcard character that would pick up net names 1-32.
I encourage you to visit the Autodesk Forums where you can get help ...
2
Since I want to shed heat rather than contain it, what are the best
ways I can to improve the spacer and/or PCB to better facilitate the
transfer of heat from the PCB to the spacer and case?
Try and use a different material if possible, I'd imagine that you chose phenolic because of its electrically resistive purposes. If heat needs to be conducted away ...
2
9600 bps equates to about 0.104 milliseconds per bit (1/9600).
The signal speed on a PCB microstrip (external trace) is calculated by:
where Vs is the velocity of the signal, c is the speed of light (11.8 inches per nanosecond), and Ereff is the effective dielectric constant (about 2.92 for FR-4).
The signal speed on a PCB stripline (internal trace) is ...
2
You'll need to take the transistor off the board and follow these steps (for an NPN transistor):
Step 1: (Base to Emitter)
Hook the positive lead from the multimeter to the to the BASE (B) of
the transistor. Hook the negative meter lead to the EMITTER (E) of the
transistor. For an good NPN transistor, the meter should show a
voltage drop ...
2
Page 16 is labeled "mechanical data", and describes the package itself.
Page 17 is labeled "land pattern data", and shows what corresponds to the footprint you've downloaded:
2
it is recommended not to use power plane as reference plane if
possible.
To add to bitsmack explanation of the challenge of reference plane switching, I'd like to add an illustration on why the plane stitching is important. Take a look at the nice animation of electron "movement" in a transmission line:
The image source is from Wikipedia. Note that the ...
2
If you have a power plane on the third layer, this becomes the reference plane for the bottom layer. This isn't a large problem: you just need to place a stitching capacitor near each trace where it transitions from top to bottom. These capacitors will only be connected to vias; one to the Vcc plane and one to the ground plane. (This is shown in the doc you ...
2
Another way of saying what @DKN has written correctly, is the goal of a decoupling cap is to :
minimize the area enclosed by the loop current for a pulse with fast rise time.
minimize trace inductance (~0.5nH/mm)
two inductive vias (~1nH) close together sharing the same current pulse in opposite directions will have some mutual inductance that tends to ...
2
It is because in the second case the current travels down each via in OPPOSITE directions. Assuming that:
the vias are placed right beside each other, and...
that the currents are equal (i.e. the capacitor is only decoupling only that component pin and the component pin is only being decoupled by that capacitor),
then the magnetic fields generated by each ...
2
You won't need vias to connect your IC grounds to a ground plane. You are using through hole parts. The holes are plated, and basically they are oversized vias. Any pin that connects to ground would automatically be connected to the ground plane - provided that you manage to define the copper area as a ground plane.
As for creating a ground plane in ...
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