New answers tagged

1

With this being my first PCB, I wanted to know if it was standard practice to make the entire top signal layer into a ground plane solely for the two ground pads that I have for the audio connectors which pour into the plane? While it may seem excessive, it doesn't add any additional cost to make, but it does have a function to create one continuous plane. ...


2

As @Troutdog says in the comments, you need a component (schematic symbol and footprint) to provide connection points for 5V IN, CH0, CH1, and Ground. When I want to have points to solder wires to a board, I often use a 1 pin component on the schematic, and a footprint consisting of a single pad on the PC board (You may have to make both the schematic symbol ...


0

If you are sure that these pins do not need to be connected anywhere then go to Project>Project Options. On the tab "Error Reporting" find "Nets with only one pin" and change it from Error to Warning.


0

The problem probably lies with the component/footprint. Double check the component in the library and make sure it has 3 independently named pins. Make sure that the foot print also has 3 independently named pins and that they match the sch component library.


1

There are a few other ways to separate out connections. One is a net tie The other is a keepout trace


-2

The RC time constant across the switch is 10 us relative to a short bounce time of 1ms for a button or 10 ms for toggle switch indicates R is harmless for the decay time of 0.47 ms but may be slightly low so 10k might be more appropriate to allow increases from mechanical aging. In gold plated switches if a large e-cap were used to debounce then may reduce ...


3

If you place the cap and resistor close to the MCU, then the trace connecting to the switch will also carry the transient spikes and noise from the bouncing event. If you place the cap and resistor close to the switch, the bouncing transients will be filtered out, and the trace connecting to the MCU will have a lower dv/dt. As others have said, given the ...


3

I will not make any difference to the debouncing. If you suffer from OCD like some of us though put it close to the switch. The bouncing contact may produce EMI.


1

You need to change the net connection rules of your ground pour. Select the ground plane -> Properties panel. Select some option other than 'Pour Over All Same Net Objects'. You can also create a 'Polygon Pour Cutout' (Place->Polygon Pour Cutout) around that trace, as changing the above rule might cause things to not connect to the ground pour nicely ...


0

I am working with Eagle 9.6.2. Eagle has changed quite a lot in the last 5 years so there may be some differences. Disable the option to place the vias that are not 1-16 in the first place. In DRC-> Layers remove the via options that you don't want. After that it should not be possible to use it. Check the Manufacturing->Drills tab. All holes are ...


1

There's no standard per say, but in recent versions of Altium (20, 21, and maybe 19) you can specify the layer type. See: https://www.altium.com/documentation/altium-designer/working-with-mechanical-layers-ad This additional layer data allows Altium to manage layers by type rather than just layer numbers when importing the footprint into a PCB. This allows ...


0

How do you plan to pre-place your "boards"? External connectors? On one edge? Two edges? First assignments? Example : Two layers for supplies distribution (+5V, GND), as you have some connections... One layer for signals, One layer Gnd1 for ground signals (quasi no current, in general weak current). Some cautions to follow: (not limited) Well and ...


0

I strongly suggest that you have vertical tracks on one layer and horizontal on the other rather than the somewhat haphazard layout that you currently have. This may seem inefficient but it’s essential for dense PCBs, and you can eliminate non-essential vias once the initial tracking is complete. The inductance of vias is important at speeds in the tens of ...


0

Have you considered just keeping the ESP8266 in deepsleep and having the reed switch cause it to wake up? Here's a door alarm project using an ESP8266 which does that: https://github.com/chaeplin/esp8266_and_arduino/tree/master/_48-door-alarm-deepsleep More discussion here: https://github.com/esp8266/Arduino/issues/1488#issuecomment-205113504


3

The target of this is saving space on the PCB(or trying to do it). You need to connect 7 conductors there (the two superspeed pairs, and classical USB1/2 signals and at least ground), probably 8. I don't think you'll get that any more compact than with a vertical USB-C connector.


4

What kind of ADC noise is this? Notice how there are apparently non-random "bands" of amplitude on that noise, around which many samples vary by only a small amount. I have draw some lines on your original plot, to show them: When I see this type of non-random pattern, the cause is not analog noise getting into the ADC, but is "digital" ...


2

Any dielectric between any two conductors is basically a capacitor, and the capacitance is determined by the area of the conductors, the distance between conductors, and the dielectric material between them. This also applies to wires in cables and copper wires on PCB is no exception - basically a PCB that has a solid copper plane on both sides is just a ...


5

The capacitance formed between copper planes in different board layers is typically much smaller than the capacitance from discrete capacitors. but it has a very low parasitic series inductance and therefore is the most important capacitance for frequencies above a few 100 MHz. This frequency range is important for decoupling fast ICs or for handling ESD. ...


1

The larger device is suspected to cause the kernel to switch it between modes of operation/memory banks, which puts it into an unexpected state after the reboot. This causes reads to either return unexpected data or nothing at all. A reset command, specially 0x66 0x99 seems to work for this device.


1

Basically, a digital resistor is a component whose value varies in discrete bumps. An analog resistor is the fundamental component which has a "certain" resistance value and which can vary continuously between two extremes under the influence of a voltage, for example. If no "influence variable" is present, it is a "fixed" ...


0

So after several feedbacks from good people, I made several changes in terms of consistency, naming, placing. Thank you everyone who took their time to help me out. I removed ground plane from top layer, decreased number of connections in bottom plane to one and decrease size of mounting holes to 2.5mm. You can see final layout below.


2

Suggestions on the silk: Some of the text is close to (or overlapping) holes in the solder mask and most board houses will clip those; text on the upper-right mounting hole is an obvious example, the body outline of the NE555 inside the pads is another. The pin descriptions on the right-most connectors are possibly too close to the board edge and may be ...


1

There are some acute angle pad entries that might create acid traps during PCB etching. Take a look at the red circles. You might also read this Cadence application note: https://resources.pcb.cadence.com/blog/are-acid-traps-still-a-problem-for-pcbs-in-2019-2


0

1- You should think of terminals and connectors while designing your PCB, you should also think about the width of traces since those traces will support high current (8A per every trace) and I'll give you an example: Every battery pack will be connected to the PCB by a XT-60 connector. Then connected by traces with largest width possible (say 10mm) and then ...


0

Factors that contribute to the delay from one signal to another include but aren't limited to: Difference in propagation delays of the PCB traces. Difference in propagation delays from the chip's transceivers to pads. Difference in when the outputs change. The Intel app note says the chip adjusts the third, and the requirement "Propagation delay of ...


2

Planes are "negative" layers. In the simplest situation they are all connected to one net. You can draw lines on the layer to split a plane and connect a certain region to one net and another region to a different net (for example, +5, +3.3 and -5V). The plane is assumed to be entirely copper except where lines, pads connected to a different net, ...


1

Solder pads for SMD components with leads (i.e. SOIC, SOT, QFP, etc) should in general be a little wider than the component's leads and quite substantially longer. The extra length allows excess solder to go somewhere, makes the bond stronger (due to the solder fillets at either side) and makes hand-soldering the part possible in the first place (since you ...


2

Option 3: Pigtail out all wires off the board with high gauge (like AWG22 or AWG18, whatever fits in the through hole) so everything is easily accessible. *maybe an inch or half inch of wire. If your ground is on the 1 or 2 layer, you could just scrape off the soldermask to get to it or solder to another component ground. Keep in mind this will add a small ...


4

Unfortunately, the common pin 6 needs not just a wire, but a fairly low impedance one depending on how much imbalance current there is between Vout+ and Vout-. If your common ground is nearby this shouldn't be a problem. So a couple of ways to deal with this. Option 1: Carefully drill the PCB with hole for the missing pin, making sure your inner layers aren'...


5

This looks ok, one other thing to note is you if you want to prevent leakage beneath the input trace to the amplifier need a guard trace directly underneath it. The problem is FR4's impedance is something like 10^8 Ω (also depends on humidity) most opamps are much higher than that. So the current leaks out (or in) through the FR4. The guard trace keeps the ...


1

The best advice I can offer here is to copy the layout pictured in the datasheet (page 23). Do your best to copy that. Also, read all the layout advice on this page carefully. These guys know what they are talking about. It is not an issue to have these on the same layer. Parasitic capacitance will be minimal. (Capacitance is more of an issue having ...


1

I'd be more concerned that your basic circuit is wrong: - Look at the direction of the bulk diode inside the MOSFET. Better view: -


0

Consider the following circuit: simulate this circuit – Schematic created using CircuitLab Any current though Circuit A must pass trough the via. This will create a voltage across the via that is also shared with Circuit B. If circuit A use allot of power and circuit B is attempting to do an accurate measurement you will create noise on circuit B. ...


1

After some time, I sort of found out what was wrong above and why the circuit wasn't "working". So I'll just answer my question. It was not problem with the circuit but the LED used. On Proteus, you can select the kind of LED. Above I unknowingly was using a digital LED. This means it either turns on or turns off. I don't exactly how the forward ...


1

In the Artwork Control Form, Double-click the layer named "TOP" then it will become editable. Type the desired layer name, then hit Tab (or Enter, or click outside the name field) to commit the name change.


0

Based on this video, yes it will create a EMI issue, since there is not GND under (or over) the VCC/power traces. This will cause the return currents (if the VCC/power has ripple and its not pure DC) to "go around" to connect with the GND, like this: 22:12 of the video The more you put GND under your traces and Power lines, the better the EMI.


0

You have made a nice loop antenna, whether it becomes a problem will be determined by the currents on the antenna. Because the currents will enter at one connector and go both ways around to the 'exit connector' it may not be a problem. The vias probably don't make a much of a difference.


1

What you suggest is ok, but I’m not sure why you feel the need to dedicate an entire layer to the GPS signals. You’ll want to keep the GPS antenna as short as possible and have a little clearance from other signals but there’s no more of a problem having signals on the same layer than having them on an adjacent layer. But if you want to lay your board out ...


3

The GPS antenna should be on the top layer, and the GPS receiver should be on the bottom layer. If you can, get a through hole component for the antenna connector (either that or keep it on the same side of the board), this will allow you to keep the trace running from the antenna connector to the Ublox a continuous transmission line (the M9N needs 50Ω) ...


1

If you open the datasheet from where you copy-pasted those two pictures, next to them is the example PCB picture which basically verifies your guess how to wire it. Yes, route the traces via NC pins.


2

Vias should generally be direct connect (i.e. no thermal reliefs). If you absolutely need thermal reliefs on vias (i.e. if you plan to solder wires to them for test points) then go with horizontal/vertical connects rather than 45 degrees. You can change these settings in the Polygon Properties dialog.


2

While the input signal is not an issue as long as you have clearance, you will have problems. Your traces are way too thin on the caps and diode. Most buck will suggest using power planes to route the switching node with the lowest impedance as possible. The Caps, and Diode and inductor should be placed as close as possible to the switching circuit. The ...


1

To answer your question, you will need to (a) simulate the filter with an EM simulator, to see where the currents in the copper are largest (often at the corners of the traces) or better yet (b) build the filter and measure the temperature rise when it’s used at high power. A multi physics type of simulation would find the current maximums and estimate the ...


1

I feel foolish, but I just needed to print it anyway, the pdf and printout does indeed show the hole...


3

I think Guy Inchbald has it covered well. I had one thought in addition: If you run two traces to each LED (anode + cathode) to make a tight supply-return-pair, you will have almost no loop area and be safe from differential mode emission and interference. However, as the LED has no other potential reference other than those two traces, the trace pair is a ...


3

1 MHz is fairly tame, not much above audio from the perspective of EMI. For example it is well below the self-resonance of most discrete components, and its quarter-wavelength on a PCB trace is around 4.5 m. My instinct is to slug the FETs to limit their output bandwidth to around 5-10 MHz. That looks a little lower than the LEDs' maximum bandwidth, which ...


2

I wouldn't deviate from the reference design, at all. If that antenna doesn't suit your needs, you should find a difference reference design :) For example, this antenna is a flattened approximation of a helical (coiled spiral) design. So, it's not just the length of the antenna, but also the depth of the pcb substrate, which is critical to the design. The ...


1

Either search for the required footprint in the supplied libraries or online libraries. If you can't find one suitable, then you have to generate one yourself. It's not too difficult and it is a useful skill - you'll find yourself need a specific footprint at some stage.


2

Pay attention to the dimensions of the antenna elements. You should copy the reference design exactly, and not modify it. The antenna traces should be at the external layers, Top and bottom.


0

A few things: It's not clear if your PGND/GND should be tied together If the P1.1 has isolation then PGND and GND should be separate, if not then they need to be tied together. I can't tell because there is no information on the 3A Buck module Q1 is a low side switch and is facing the wrong direction (the diode will always conduct even if the switch is off)...


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