New answers tagged

3

Your initial impression is incorrect. Here is what the impedance of various capacitors in the same package looks like. source In order to get a sufficiency flat power supply impedance over a wide bandwidth, one needs to use a selection of different capacitors.


3

There may be some small benefit. Using a Murata's SimSurfing tool, I graphed the impedance vs. frequency curve for a 2.2uF 0402 (1005 metric) MLCC compared to an 0.1uF one in the same package. The 2.2uF cap is shown in blue in and the 0.1uF in green: As you can see, the point of resonance is higher in frequency with the 0.1uF, as would be expected of a ...


1

Indeed there is. The most obvious one is cost. Ceramic capacitors of different values in the same FOOTPRINT (not necessarily package since height may vary) do not cost the same. Beyond that, ceramic capacitors have different impedance curves (due to the different parasitics as you mentioned) and DC bias curves for each combination of capacitance, dielectric,...


1

With FR4 50 Ohms tracks just under 2:1 track width:height above ground plane so 2mm track means about 1m dielectric thickness if DK=4.4 Adding Coplanar grounds with 0.49 mm gap increases height so w:h=1.25 or FR5 thickness of 1.6mm 50 Ohms means a ratio of sqrt(L/C) so 0.12pF/mm is reading a bit high with 0.3nH/mm, not much, especially C3=1pF which has ...


2

Can those soft curves on the upper ground plane that KiCad adds automatically around the pads of the capacitors affect the behavior of the waveguide? Above 10 GHz, they might. In Altium I can add a "keep out" to prevent these features from being produced. You should be able to do something similar in KiCad. Have I added too many viases around the signal ...


4

thermal/vibrations stresses in the environment. directly contradicts have the user be able to take the chip out to replace it Clearly, if you need potting for your components, you don't want your user to be able to take out parts. You'd normally just do this with a firmware update routine built into the firmware you deploy. For example: Your firmware ...


5

A couple of things. I assume you mean "DIP" not "PID" for the existing package. That socket you link to is not for mounting TQFP, it is for PQFP packages, also a very old package. In my opinion, there isn't a good socket for TQFP packages, any you find will be expensive, have a large footprint and be unreliable - especially if you have much vibration. If ...


1

I don't design these kinds of antennas and my books on the topic are at work, so I'm not sure, but you will find you already got into trouble with your length calculation. You used the speed of light in a vacuum to calculate the length. (notice the 'in a vacuum' part). On a PCB the wave will travel more slowly. Your microstrip tool helpfully points out that ...


0

The Via not assigned to any net(M3).So, you getting "Un-Routed Net Constraint" Error. You can assign the net (M3) by following steps Select all Vias, which is not assigned any nets. For that, a.**Right click on the via->Find Similar Objects** b.**In the Find Similar Objects window, Modify NoNet -> same-> OK** Now all unassigned Via selected ...


0

Another (I think better) way to decrease the inrush current is to PWM the motor voltage, starting at 0V and increasing it slowly. The PWM frequency should be high enough so the motor cannot 'keep up'. A not audible PWM frequency of >50 kHz will most times do. A way to determined how slow to increase the PWMed voltage is to look at the rise time of voltage ...


1

1) since you're only dissipating about 0.2 W I would say this is more than OK assuming that this PCB isn't in a very hot environment. It is possible to calculate the thermal resistance (to ambient) using tools such as those on TI's website. 2) Possible: yes but I would not choose to do that! What you are then doing is temporarily giving the MOSFET a higher ...


3

So I found what the issue was, I made a stupid mistake between the schematic and PCB so make sure you always triple check everything before sending the board out for manufacturing. I miss-connected VDDA to GND and VSSA to VDD in the schematic and only noticed it after designing the PCB and me being stupid I got distracted or whatever and never updated the ...


1

I don't think this will cause any issues. Although technically this is a loop, ground loops are usually a problem when some device has multiple "ground" connections which may differ slightly in potential. This won't occur here since there are no devices in the loop.


1

I've read many advantages/reasons on different forums about these mounting holes with vias but I did not see the reason that I am using them for. With plated mounting holes, if the board is going through a wavesolder machine during the assembly process, all these holes need to be masked with a piece of kapton tape to prevent the solder to get into these ...


1

From UL840 (Jan 6 2005): ** 6300Vdc/ACrms, Polution Degree IV, Material Group III (CTI 175 to 400) = 320mm PD IV is a conductive or wet dust. If you can go to Polution Degreee II (limited condensation and non-condutive dust) by controlling the evironment some way, then that reduces to 63mm. If you can use a material with a higher CTI as well, then that ...


1

SoC ‘s that look like the two on your photo are ASIC’s and thus are an Arm and a Leg to buy. speaking of ARM’s .... TI has licensed CORTEX from ARM to put in their Open Multiple Architecture Platform called OMAP and may be developed on a BeagleBoard from DigiKey. Unless you have deep pockets, here some of what the big OEM’s use for SoC’s from a half a ...


7

I am sorry to be the bearer of bad news! There are a few things that stand out. In addition, even after these problems are corrected, there's still going to be a lot of learning and analysis to do. Please don't take my suggestions as criticism; RF is tricky :) Also, there have been hundreds of books written on RF. I can tell you some things to look for, but ...


1

The connector pins and wire are not your major concern. The traces would have less “ampacity” unless designed for greater max current in event there is no PTC or fuse protection. Web data exists for these trace “ampacity ratings” as well as free Saturn PCB software. Ohm’s Law defines each power and return voltage drop or power dissipation per unit. If you ...


6

It's not only the dielectric strength that you must worry about, but also the spacing between connectors. As you know, high voltage tends to arc. Because of this, you won't find connectors that are closely spaced in high voltage parts, even with high dielectric strength materials, per IPC spec, there is a minimun distance even if there is insulation. If ...


1

I just looked around and I found something on the Altium website. Maybe this can help you. Here you can also find more information about PCB design. To place a 3D Body and populate its contents in the PCB Editor, select Place » 3D Body from the main menu, create its object shape and choose the Generic option as the 3D Model Type in the Properties panel. The ...


1

Defining the Board Shape from a 3D Body (https://www.altium.com/documentation/18.0/display/ADES/((Defining+the+Board+Shape))_AD) This feature redefines the board shape based on a surface (face) of an imported 3D STEP model. It can be used to quickly create a complex board shape and helps integration between electronic and mechanical design areas. This is a ...


0

Usually you want them 1/10" or more for easy soldering (and soldering). More height also helps to put some thermal resistance between the transistor and the soldering iron. I once made an assembly house put a transistor 1/2" (about as high as it would go) because I needed thermal resistance between the transistor and the board. The board had some sensitive ...


2

If it's a hobbyist project, just follow what you see on existing commercial hardware. You want it to sit far enough above the board so that the leads are not stressed, either because they're too short and everything is jammed together in assembly, or because they're too long and the part is moving from shock and vibration. Ideally TO-92 transistors should ...


6

This might be the drawing for SOT804-4, which you are looking for. The land pattern is on p.3 . The second row isn't soldered to the board, if I'm reading the drawing correctly. I'm guessing, each oblique pad in the second row is connected to the pin on the outer row. So, the second row would be signals, not all grounds. If you have the an IC in your ...


0

I think the information you are looking for is at the end of Table 3 in the datasheet. This table lists all of the pin connections for the QFN package, as well as the exposed die pad.


3

Page 3 of that document gives you a land pattern. You don't have to guess. In general, data sheets give you recommended PCB layouts, or refer you to documents (like that one) that give it to you.


1

The idea with guard rings is to prevent leakage current. FR4 has a volume resistivity (varies from manufacturer) as low as 10^14Ω cm. What you have is most likely sufficient for the leakage current you may have, but since it's easier to run traces than to calculate the leakage, I'd add another one around the pins of the dip switch. Make sure you pull the ...


2

You won't need vias to connect your IC grounds to a ground plane. You are using through hole parts. The holes are plated, and basically they are oversized vias. Any pin that connects to ground would automatically be connected to the ground plane - provided that you manage to define the copper area as a ground plane. As for creating a ground plane in ...


1

Let red be the slot width and purple be the slot length, then have the width be determined by the required clearance corresponding to the applied high voltage. have the length and shape of the slot be determined by the required creepage corresponding to the applied high voltage. Choosing the width equal to the required clearance distance assumes the ...


0

The design files are made in Altium Designer. You'll have to open those in that, or you'll have to somehow convert the files to something Eagle would open. It may be possible, but from a quick google, this seems to be a long and painful process. However, looking at how simple the NodeMCU board is, it shouldn't take you long to "just" replicate it from the ...


1

The information displayed by OrCAD depends on your current "Application Mode" ("general", "etch", "placement", etc) and the options you have selected in the "Find" dialog. This is difficult to explain; let me show you some screenshots. Let's assume you are in "general edit" mode. Starting with everything in the "Find" dialog selected (notice the red ...


2

Another way of saying what @DKN has written correctly, is the goal of a decoupling cap is to : minimize the area enclosed by the loop current for a pulse with fast rise time. minimize trace inductance (~0.5nH/mm) two inductive vias (~1nH) close together sharing the same current pulse in opposite directions will have some mutual inductance that tends to ...


2

It is because in the second case the current travels down each via in OPPOSITE directions. Assuming that: the vias are placed right beside each other, and... that the currents are equal (i.e. the capacitor is only decoupling only that component pin and the component pin is only being decoupled by that capacitor), then the magnetic fields generated by each ...


0

It could also be this issue: For example a resistor. The resister footprint is not matching with your schematic. In the schematic, the resistor R1 terminals were named like R1-1 and R1-2. But, footprint pads name not 1 and 2. Go to the corresponding library and Edit the footprint pad name.Then it will be Okay!


1

In those cases the voltage difference will be same or less so it's also good. Remember FR4 is good for over 10kV per mm (in the second answer), so low voltage mains circuits (<1kV) are perfectly fine across the thickness of the pcb (which is typically 1.6mm)


3

The pattern is on the copper layer. It appears they have used the "hatched" pour option in the PCB design software with an unusually low fill. You can see the regular pattern of the pour being broken up by tracks and one area where the pattern is missing completely, presumably because the "remove dead copper" option was used when making the pour. It looks ...


2

it is recommended not to use power plane as reference plane if possible. To add to bitsmack explanation of the challenge of reference plane switching, I'd like to add an illustration on why the plane stitching is important. Take a look at the nice animation of electron "movement" in a transmission line: The image source is from Wikipedia. Note that the ...


2

Page 16 is labeled "mechanical data", and describes the package itself. Page 17 is labeled "land pattern data", and shows what corresponds to the footprint you've downloaded:


1

You should use a PCB trace width calculator, I think you will find for 10-15A 40mil is a bit undersized. 10A on a 1 inch trace with 1oz/in copper will see a 100C temperature rise. https://www.4pcb.com/trace-width-calculator.html Also depending on what and where this is being used, your distance between high voltage traces to low voltage or isolated signals ...


2

If you have a power plane on the third layer, this becomes the reference plane for the bottom layer. This isn't a large problem: you just need to place a stitching capacitor near each trace where it transitions from top to bottom. These capacitors will only be connected to vias; one to the Vcc plane and one to the ground plane. (This is shown in the doc you ...


0

laminar copper isn't pretested for resistivity as it develops different temperature ranges it will show a non linear resistivity course. such a temperatures are stated in order the max temperature achieves the final thermal adequation of the layers leaving the original pcb diagrams for the very long term use...


7

Many things go into designing the width of the PCB trace, including temperature rise for current. Others are voltage drop, impedance, PCB fab capability, cost, packing density. However, temperature rise is rightly one of the 'do not exceed' specifications. A rule of thumb is just that, something you should follow most of the time. You will always be able ...


4

A common mode choke acts as a low impedance path for normal (wanted) differential currents flowing to and from a load. For these currents, the net magnetic field in the ferrite-core is largely zero. Or, put another way, the ampere-turns for the forward load current is cancelled by the same ampere turns flowing back from the load. This means that copper ...


3

If you understand creepage is the ionic breakdown of a good insulator due to the accumulation of dust and humidity, then you will understand why an air gap is good. You may need 2 connectors. Clean air is about 5kV/mm between smooth parallel surfaces. Plastic can be >10kV/mm. The highest level of indoor contamination of residential humid dust on the ...


5

So, could I find a distance between both connectors in which the VCC+ connector and VSS- connector will be safe from breakdown? Yes, but it's already been done for you in the IPC specs the table below shows this. It might be best to use two separate 1 conductor connectors, instead of finding one that has both (although the connector wouldn't be keyed for ...


1

Can you 3D print a shroud (audio waveguide, whatever) that snaps onto the PCB and interfaces the outside world to the microphone? If you're not Bose you'll probably lose a bit of fidelity, but I suspect not much.


0

You're right to be concerned. One source I found gives a formula for the cut-off frequency of the 1st higher-order mode in microstrip: $$f_c = \frac{c}{n\left(2W+0.8h\right)}$$ However, the microstrip line will become dispersive (the propagation velocity will start to vary with frequency) well below the higher-order-mode cut-off frequency. Microwaves101 ...


1

For maximum heat transfer, use an aluminum (or better, copper) spacer, a mica washer, and thermal grease. You might be able to get by with a thermally conductive silicone pad, but those don't tend to be mechanically strong. "Silpad" is a brand name you could use to start your search.


0

You have slipped a digit. Or three. You have done your computation by plugging "0.2" into the formula while using m/s for \$c\$. If you use consistent units then for the first mode you get \$\omega_{cm}=\frac{1 \cdot \pi \cdot c}{(2.1)(0.2\cdot 10^{-3}\mathrm{m})} \simeq 2.2 \cdot 10^{12} \mathrm{\frac{rad}{s}} \simeq 360\,\mathrm{GHz}\$ This passes my ...


2

Since I want to shed heat rather than contain it, what are the best ways I can to improve the spacer and/or PCB to better facilitate the transfer of heat from the PCB to the spacer and case? Try and use a different material if possible, I'd imagine that you chose phenolic because of its electrically resistive purposes. If heat needs to be conducted away ...


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