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You will hate yourself if you do stack up number two ;) Maybe that's harsh but it's a going to be a PITA reworking a board with all internal signals. Don't be afraid of vias either.
Let's address some of your questions:
1.Signal layers are adjacent to ground planes.
Stop thinking about ground planes, and think more about reference planes. A signal ...
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The important difference is this.
Core is a layer of FR4 with copper either side, that's made in a core factory. The layer of FR4 is formed between two smooth foils of copper, to a specified thickness.
Pre-preg is a layer of uncured FR4, that's used by PCB manufacturers to glue together etched cores, or a copper foil to an etched core. This means the ...
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There is no such thing as THE best layer stackup. If you read carefully, the stackup with grounds on outer layers is said to be best from EMC perspective.
I don't like that configuration, though. Firstly, if your board uses SMT components, you'll have a lot more breaks in your planes. Secondly, any debugging or rework will be virtually impossible.
If you ...
17
But for a mechanical strain relief for over stress on users with kids and USB plugs getting torn out, it is excellent.
The main board has a good 3 point screw hole mount to eliminate torsional stress on brittle ceramic parts and the breakaway allows more board bending stress to occur at the gap without stress on the ceramic chips. Meaning OK for open board ...
answered Apr 10 '17 at 12:57
Tony Stewart Sunnyskyguy EE75
90.3k2 gold badges33 silver badges134 bronze badges
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Yep, and it's pretty straightforward. Just click on the Info button , select the airwire you want to hide, and click on the "Airwires hidden" checkbox. All airwires on that same net will be hidden.
Obviously this is a do-at-your-own-risk. You'll have to remember to explicitly un-hide the airwire later to do the routing.
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This split up arrangement would help from noise traveling between the modules?
If you have multiple power voltages and a 4-layer board you don't have much choice. You have to deliver different voltages to the different loads. Whether it reduces or increases noise has a lot to do with the details of how you lay it out, it's not possible to just give a ...
13
I suggest you combine the two methods. Drill a hole near the traces and thread a thin bare wire through the board, lay it along the exposed traces by a few mm and solder it on both sides.
If you don't have such a wire handy, just strip a piece of stranded wire and use one of the strands
Nobody will notice unless they look very carefully, and it will be ...
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Ah the horror of trying to make DDR work in two layers :) The long answer is of course to learn about signal integrity and try to understand exactly what you are doing. I have seen this done before, and even pass EMI but with many caveats. First there was only a single DDR part. Second the controller was carefully designed to route out onto all signals in ...
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Tip. Keep ground as an inviolate layer, and use the 3 other layers for signals and power.
Treat power as a signal. While there are theoretical benefits to having a power plane, it is rarely worth it. The cost of dedicating a whole plane to power is too high, in terms of real estate. The time saving of 'not having to think' about power distribution is ...
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As Dave posted in his answer (+1), you need to enable the layers in the DRC. Here's an example:
And from the EAGLE help file (which is an excellent resource by the way):
Layers
The Layers tab defines which signal layers the board actually uses,
how thick the copper and isolation layers are, and what kinds of vias
can be placed (note that this ...
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If you want to make 4 layer boards, use a real tool, not a toy. Design Spark PCB is easy to learn. KICAD is a bit more difficult. Both are free, and support unlimited layers and pins.
As has already been said PCBs come in lots of layer counts. The same can be said for soldermask color, material, thickness, copper weight, and finish.
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The short answer is you're going to be fine, route it above VCC and make sure you have some VCC to GND decoupling caps near your chip. Plus your route is pretty short at 600mil, I've seen some people do terrible things to USB routes that still end up working :)
I think the best way to understand this is to consider where your return current will flow. ...
11
When TX switches low-to-high, the current flows like this:
Power supply Vcc -> PCB Vcc plane -> U1.Vcc pin -> U1.TX pin -> U2.RX pin -> U2.Gnd pin -> "return path" -> PCB Gnd plane -> Power supply Gnd
It's great that you understand that what we call the "return path" will be the nearest plane (in this case the Vcc plane). This makes sense as the fields can'...
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There are two aspects of a ground plane: its performance, and its appearance. The first is important. The second is not. Unfortunately, many people starting out concentrate on the second, to the detriment of the first.
A ground plane should be as big as it needs to be. That is, it should be present at or near* every connector, every IC, every supply ...
10
You can specify a design rule for that component:
Design > Rule > Placement > Component Clearance,
Add new rule like this:
Advanced query: InComponent('D1') //assume the component is 'D1'
Constraints:
Min Vertical Clearance 0mil
Min Horizontal Clearance 0mil
Then Altium Designer will not check this component's clearance.
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Fritzing only supports two copper layers, you can see an example at the
Fritzing's View options tutorial and it only has the copper 0 and copper 1 layers available for display. As for the maximum numbers of layers a PCB can have I'm not sure, but a local company I've used in the past (but not for this many layers) Entech Electronics advertise up to 26 ...
10
SPI bus at 50MHz can easily run a couple of inches thru a few vias without hitch. Wavelength of 50MHz is 6 metres but realistically because fast edges are used you need to think ten times faster. Even so that's a wavelength of 60 cm. Rule of thumb is keep tracks smaller than a half of a quarter wavelength (other folk will use other rules of course) and this ...
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I don't see any reason why you can't create a footprint with overlayed pads on top and bottom going to different pins. Just specify the hole as unplated. If you avoid drilling one of the holes (make it an SMT pad) you may be able to avoid all DRC errors with little fuss (otherwise it may complain that the two drilled holes have insufficient clearance).
...
10
For what it's worth, at my last two jobs I've had the pleasure of working with a super-talented electrical engineer (different person at each company), and in both cases the engineer's preferred design approach was to use one single ground plane for everything. Yes this runs counter to the conventional wisdom of how to lay out circuit boards, and they freely ...
10
The primary advantage of a Manhattan route is that it can always be completed. You just need to have enough board area to accommodate all of the traces — but otherwise, you'll never find yourself unable to complete a route. This can be important if you need to get a layout done on a fixed schedule — the amount of work is roughly proportional to ...
9
"best" depends on the application. Theres really two questions to address in your post
"Conventional" (signals on outer layers, planes on inner layers) VS "inside-out" (signals on inner layers, planes on outer layers).
An inside-out board will have better EMC performance but it will be much harder to modify when you realise you screwed up the design, will ...
9
Generally you don't need separate planes for power. If you have a good solid ground everywhere (you do want a plane for that in many cases), then the only issue for power is that the voltage drops due to the power current and DC resistance in the traces are acceptable. Don't worry about high frequency AC impedance in delivering power that much. Instead, ...
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While DrFriedParts provided an answer to the question you asked, I feel I ought to respond to your premise, instead. Specifically, "i do know this decreases the resistance of the tracks and increases the amount of current it can handle", while technically true, is not a reason to specify HASL. Let us consider. A 1 oz copper trace has a thickness of 1.37 mils,...
9
If there is exposed copper at the edges, then the board was designed improperly.
Almost certainly whatever software you are using to design this board has a parameter that controls how close edges copper is allowed. Verify the setting, and of course make sure the software is actually checking against this rule.
The software may have not known that the ...
9
Generally Core is more reproducible than Prepreg, for both thickness and dielctric constant. It is made in a factory making core to a specific thickness.
When prepreg is assembled into the final board, which usually has a finished thickness specification, the thickness of the prepreg dielectric will have an additional variation due to the variations of all ...
9
The Gerber files do not specify the order of layers. As long as you don't use blind or buried vias, the layers can be stacked in any order.
The file names for the individual Gerber files may vary between different CAD systems, and may or may not imply the desired stack-up order.
I always included a "readme" file with my PCB order specifying the desired ...
8
I'd recommend looking at PCB Design Guidelines For Reduced EMI by Texas Instruments.
While it is focused on reducing EMI, it offers advice or answers to all of your questions except "Manhattan Routing".
Section 2.1 (about 12 pages) is about Ground and power. It includes these
useful sections:
2.1.7 Power Plane Do’s and Don’ts for Four-Layer Boards
...
8
Difference between core and prepreg is that core has cooper filled on both sides of dielectric and prepreg is just full dielectric, no copper on any side of the material.
Since you just sandwiched the prepreg between two cores, which are themselves clad with copper, the prepreg now has copper on both sides of it.
Why wouldn't return current flow on the ...
8
There are number of reasons in which you have multilayer boards, and when it comes to high speed design, DDR3 for instance, there is alot more happening than just the connections from pin to pin.
At high speeds, the physics behind electric, and magnetic feilds become a factor as well as power speed requirements. It's no longer a case of just connecting from ...
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