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4

once a second calculate/benchmar how much time that calculation takes. Wild guess: less than 200 CPU cycles. You didn't tell us anything about your MCU, but let's assume it runs at 1 MHz (that's far slower than modern MCUs usually run). Then, that's 2·10⁻⁴ s worth of power consumption. Does that matter to your application significantly? We can't tell you, ...


2

Mechanical layers do not appear on the final PCB. They are used for reference purposes only during the design process, as well as sometimes the setup process at the PCB manufacturer. The pink layer indicates the outline of the 3D body of the chip. This is used so that you, as the designer, can ensure that it does not collide with any adjacent components. The ...


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You can place a NoERC directive, if you know that this net is correct (unused pin, antenna etc).


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The use of mechanical layers (you can, and should, have many of them) is up to the user to a large degree. In a footprint, one of the main purposes is to give a visual and (enforced by rules) bounding area to prevent interference during layout. Another use in footprints is to create assembly diagrams more-or-less automatically. By adding a special string “....


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HASL works fine for PTH, even large holes, I see no reason for it to not work with castelation. It does somewhat bind you to a solder chemistry, (lead or lead-free) and also has a shorter shelf-life than ENIG


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There's not, as far as I know, a command line way to do this. You can do it be editing the .kicad_pcb file directly. Steps are: In Pcbnew, draw out an outline anywhere. You'll want to use the Add graphic line tool (shortcut Ctrl-Shift-L) and use the Edge.Cuts layer. Save this file, and close Pcbnew. Open the saved file in your text editor, and search for ...


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