New answers tagged pcb
2
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Routing traces underneath impedence controlled traces in 4 layer PCB
Yes, it is only important to have unbroken ground in the immediate reference plane.
This is L2 in your case.
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Identification of shiny metallic blocks on the PCB
I think they're some kind of 3-terminal filtering components. There's a separate middle pad visible in some of the pictures, and they have vias placed directly at the side like expected for that kind ...
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2
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Identification of shiny metallic blocks on the PCB
Could also be high reliability capacitors, which are constructed from two series connected stacks of plates, so that cracking and short circuiting which happens quite often, does not stop the ...
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5
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Identification of shiny metallic blocks on the PCB
Hard to tell from the photo, but to me they look like SMD metalized film capacitors.
Lots of different film plastics can be used, including:
Polyphenylene Sulfide (PPS)
Polyethylene Terephthalate (...
- 4,357
3
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Layout- Should the output and input traces of this hex inverter be superposed
By a massive factor (~thousands, say), more important is having a ground plane under the chip at all.
Traces superposed for some ~cm, with risetimes of several ns (wavefront ~0.5m long in electrical ...
- 24.4k
2
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Layout- Should the output and input traces of this hex inverter be superposed
You want to minimize the coupling between the input and output, so offset traces would be a good choice. However, it probably doesn't make much difference over the distance shown and the edge rates.
...
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2
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XTR116 cannot control less than ~4.4mA
I had the same issue and investigated it to get to the root cause. After some research and finally, removing the isolator chip, I identified that the problem lies within the isolator chip, which was ...
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3
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"Error: Items not allowed (keepout area..)" KiCAD
You have placed vias and tracks within a keepout area, i.e. an area where specific features are not allowed. Keepout areas are polygons that can be set to prevent the placement of any combination of ...
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4
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KiCAD DRC erorrs
You get this error, because the board setup says, that the minimal allowed annular ring width is 3,94 mils. You are using vias, whose annular ring widths are smaller than that. Namely 2,95 mils.
To ...
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1
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Identify component: SOT-23 "ADSL" "19"
I think this could be a AO3413 P-FET.
The image markings documented here match exactly, including the two numbers at right angles. The idea of this being a PFET for high side switching, also fits ...
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0
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How is a differential impedance of Ethernet signals maintained without a ground plane
Two wires running in parallel in free space have a set differential impedance that's determined only by the geometry of the cross-section of the wire pair. No ground planes needed.
That's why it's ...
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How is a differential impedance of Ethernet signals maintained without a ground plane
Differential impedance can be achieved by referencing two lines to a common ground plane (so-called uncoupled lines) by referencing them to one another and a ground plane (so-called loosely coupled ...
- 15.3k
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How is a differential impedance of Ethernet signals maintained without a ground plane
Differential signaling means there's no ground reference by definition. You can have a grounded shield around the twisted pair, but if you ground a wire the differential signal becomes single ended.
...
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Will arcing occur if the two sources are isolated?
As long as the 3.3V trace has much more than 230V (like kV of isolation if mains as mains can have kV faults) and every part of that circuit that is connected to 3.3V has isolation, then you probably ...
- 76.4k
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Optional feature in PCB layout of MMCX board edge connector. What's it for?
I would have guessed it is a stub. This is not quite the same configuration, but I just modelled the same connection on CPW with Rogers 4350 and no matter what I tried, I was always left with at least ...
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7
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Identifying this IC marked 'IAANJ'
It's most likely an MP65151DJ from Monolithic Power Systems. For reference from the datasheet (pdf):
Note the top marking of "AAN" for an active-high single switch TSOT23-6 chip. Package ...
- 1,193
0
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Verification of Gerber file layers
Use any Gerber viewer, load both designs and give similar layers, eg GTL on both designs, different colors. You will see the areas where the layers differ, since the colors won't mix there.
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Verification of Gerber file layers
I use BeyondCompare from Scooter SW because we are not allowed to upload our design to any online storage including Altium.
As BeyondCompare can compare pictures pixelwise and mark all differences you ...
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3
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Creating a test jig for a large PCB Backplate
In terms of regenerating a schematic, the netlist and parts list is the key. The manufacturer should be able to supply these if you are still having PCBs built. The combination can give you a full ...
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How to design two pieces of board in one board and then separate? in ALTIUM
Make one board but with two halves separated by notches and mouse bites to attach the two halves - see https://www.allpcb.com/mouse_bites_pcb.html.
Note that anytime you have a design like this you ...
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I can't put a solid region to bottom layer and there is a violation which I couldn't figured out
The region shown in the above 2nd screensnap is a keepout. Need to use a solid copper region so can assign net.
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3
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Identifying SMD IC on PCB
Likely LT3580 in plastic DFN package.
According to data sheet, it has LCXY marking.
- 131k
4
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Ground terminals on the laptop PCB; laptop PCB troubleshooting/repair
Most voltages in a circuit diagram are referred to a "so-called" ground or 0V. The technician is placing the black (negative ) probe at a convenient "ground reference" point. There ...
- 12.9k
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Proper layout of GND
While most answers deal explicitely with the current, I want to add another aspect.
With all assumptions in the comments, your circuit might look like this:
simulate this circuit – Schematic ...
- 3,876
1
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Unorthodox routing, vias and fills everywhere
What you have is perfectly fine.
Many folks would tend to just stitch directly from pin 14 to 15 and 15 to 16 (as you have done). Same with pin 17 to 18. There are cases where we might create a single ...
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1
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How to calculate the via fence spacing between two differential CPWG?
Yes.
Note that the lowest mode supported is 1/2 λ, so the signals being some margin below that point (for given spacing) is adequate.
The spacing between pair and coplanar ground can also be increased,...
- 24.4k
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Proper layout of GND
Yes, I would consider this bad design.
It may or may not be an actual problem depending on your application and on how much current is actually running through such spots (probably it's just a ...
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4
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Proper layout of GND
I see what you mean by, current is passing through the capacitor. Not the best.
There are several places I marked with a X, where the copper is not doing anything.
I rotated the cap 90 and increased ...
- 916
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STM32 MCU gets shorted
The first issue I noticed is that you're missing 100nF decoupling capacitors for every VDD/VSS pair, as indicated in the datasheet (refer to the attached image). This oversight could lead to issues in ...
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2
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Proper layout of GND
When designing my PCB, I noticed that all the Ground to the whole board, was passing only from a single point, which was also through a capacitor.
That doesn't seem to be what your layout snippet ...
- 88.8k
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Can you draw power from the ADUM4160 USB isolator
If not, Is there an AIO component to isolate data+power?
There are a few such as the ADuM5400: -
It has a 500 mW power converter. The output can be used to power ADCs and some other analogue ...
- 437k
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KiCad current measure header disrupts net name
In schematics place 3V3 on the right side of the jumpers too - or in PCB New- edit and change the "random blah" net to the 3V3 net. DRC will give an error about the solderpads being ...
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KiCad current measure header disrupts net name
I understand that, for small schematics where all 3.3V connections are drawn, this is appealing.
But now, lets suppose you do a bigger project, over several pages, where you use 3.3V at many different ...
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2
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Can you draw power from the ADUM4160 USB isolator
No. the ADUM4160 only isolates. It does not supply VBUS. You need to supply either VBUSx or VDDx on both sides.
Assuming you want to build a host with an isolated USB port, you can use just about any ...
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1
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Routing a PCB with no Netlist in Altium
There are two ways:
Use Place - Line (or other shapes as you like) to draw arbitrary copper. It will be placed with Net = 'No Net'. Note that primitives will pick up nets when dragged or pasted ...
- 24.4k
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What is an ideal layout for a normally-open solder jumper?
In production, zero-Ohm resistors are way more reliable than solder bridges.
That's the most important bit of advice to give. Solder bridges are not OK even for development boards/early prototypes. ...
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What is an ideal layout for a normally-open solder jumper?
I have soldered a fair bunch of such jumper pads open/close, and in my experience they are all inferior (take longer to rework) compared to SMD pads on which you can place a zero-Ohm resistor. Either ...
- 25.7k
23
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What is an ideal layout for a normally-open solder jumper?
Take this layout:
|¯¯\ \¯¯|
|__/ /__|
Just make the arrows better than I did here :D
Slide with solder left to right to close, right to left to open. Reduce the ...
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4
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What is an ideal layout for a normally-open solder jumper?
A slit circle works pretty well if it isn't too small and the gap is reasonable. It can be opened and closed a few times without much risk.
The best size and gap size depends a bit on how "gummy&...
- 379k
14
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What is an ideal layout for a normally-open solder jumper?
The correct answer is probably: there exists no ideal layout.
Or at least none which the PCB CAD and/or manufacturer will approve. Usually the default clearance area around a pad/trace is too wide to ...
- 18.1k
0
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ST7735 driver IC connection with TFT DISPLAY
ST7735 does not contain a CPU and thus does not run any firmware so you don't need to develop firmware or upload it into ST7735.
- 131k
1
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Tips for soldering some wires into a PCB
If everything is just right, soldering should be very quick. Only a couple of seconds per wire. Too long and the board ends up charred, and the pads peel off the board.
So make sure the soldering ...
- 18.7k
3
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Tips for soldering some wires into a PCB
There are some problems with old joints. There is oxidation and the original solder may or may not be compatible with what you are using - the main concern would be leaded solder (but this looks like ...
- 18.1k
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Tips for soldering some wires into a PCB
Since the board is from 2007, and you can see the solder have oxidized, you need to add some extra solder, and if you have, flux too. Be careful around those SMD components if they are needed for the ...
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SOT-23 footprint (difference between KiCAD footprint and NXP)
It all depends on how the PCB will be fabricated and assembled.
On my last PCB I used a default footprint from the alitum library for SOT23. The pads are 0.6mm by 1.15mm. So smaller than the Kicad ...
- 21.5k
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SOT-23 footprint (difference between KiCAD footprint and NXP)
I'm answering myself by collecting the very helpful comments and answers from others.
"sure; you can reproduce entirely what a data sheet recommends." (@AndyAka)
"I bet KiCAD is ...
- 12.5k
1
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Power traces in a 2 layer PCB
Really what you want to avoid is mixing the signals' fields and power's field together. Considering you are using a standard 2 layer PCB stackup, moving the power trace on the bottom layer will only ...
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6
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What are these double arrows on a schematic?
What are these double arrows on a schematic?
It looks to me like what is called an off-page connector but, it may be called something else in the drawing package originally used. You can use a global ...
- 437k
0
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Use earth as shield between high and low voltage on PCB
Consider this: many, many power supplies don't have access to a protective earth (because they use 2 pin plugs into the wall) and, they are "safe" because they use recommended distances ...
- 437k
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Use earth as shield between high and low voltage on PCB
I have seen PCBs with gnd protectors, but they are rare as they need extra space, as the clearance/creepage distance has to be maintained from L to E, then some from E to the rest of the circuit.
...
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