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9

To elaborate on @Majenko's answer, both SGMII and 1000Base-x are dual 1000Mbps SERDES pairs (one in each direction), at least until the 1000Base-X signals reach the optical transceiver. The main difference is in the auto-negotiation capabilities. In 1000Base-X, auto-negotiation is limited to flow-control (and duplex, which is not really used since it's ...

7

The first page of the datasheets says: Fully Compatible with 10/100/1000Base-T Networks Integrated MAC and 10Base-T PHY Supports One 10Base-T Port with Automatic Polarity Detection and Correction So it's a 10 Mbit/s 10Base-T device but is compatible with the other standards so you can connect them together and get operation at the lower speed. ...

7

Where is the transformer? How exactly the termination is done, and what impedance it needs to be is a function of the PHY's requirements, which then dictate a particular transformer configuration. Since the transformer is integral to termination, we need to see it. You should really show everything from the PHY all the way to the RJ-45 jack. Your ...

6

Many PHYs do not have MAC addresses, in particular the cheapest ones as you need to pay for a block of MAC addresses and they leave that up to consumer. Example: the popular (at least among hobbyists) ENC28J60 does not have a pre-programmed MAC.

6

(promoted from comment to answer) These addresses are used for PHY CONTROL frames only, not for normal data frames. As far as I understand such frames they are not destined for a particular node. I suspect that the actual address is unimportant, and the choice of two addresses is only for debugging and testing (so you can see from which of two sides a frame ...

6

From the datasheet Fully Compatible with 10/100/1000Base-T Networks Integrated MAC and 10Base-T PHY Supports One 10Base-T Port with Automatic Polarity Detection and Correction Supports Full and Half-Duplex modes So, it is 10mbps FD (and yes, 10baseT supports full duplex, at least some cards do) and, as all 10baseT devices is compatible with ...

6

Most Ethernet systems are made up of a number of building blocks. The two most important are the Ethernet MAC Device (the device that actually makes and receives Ethernet frames), and the Ethernet PHY (PHYsical interface) device - the device that connects you to your wires, fibre, etc. These two devices are connected using a Media Independent Interface (...

5

I would simply put an RJ45 MagJack on your circuit board right by the PHY. Then use an internal CAT5 cable to go to a panel connector. The panel connector could be one of these (although other options exist). The above pictured connector is an inline coupler that permits Ethernet to pass through into an enclosure and maintain an IP67 rating. If ...

5

Basically there should be no difference what PHY You'll use, since the low level driver is written separately from all the TCP/IP stack itself. At least I am sure this is done in LwIP, since I use this stack with Micrel PHY - had to write my own initialization setup stuff.

5

MAC addresses have nothing to do with the PHY layer. These are relevant in the MAC layer, which is of course why they are called "MAC" addresses in the first place. Every ethernet MAC is supposed to have a globally unique 48 bit address. I suppose it would be possible for a manufacturer to create MACs with built-in addresses and then serialize them in ...

4

Provide the right resistances on your side of the transformer and put the jack, transformer, and PHY as close as possible to each other. If everything is within a couple inches there is nothing to worry about.

4

Since OP has not mentioned the PHY being used, taking Micrel KSZ8021RNL/8031RNL as an example.Please look at the electrical specifications of the PHY . You can see the differential output measured after 1:1 transfer lies between min. 0.95V to max. 1.05V, which is not the -ive voltage. For more details of the PHY electrical specification you can look page #...

4

Typically, a set of MII lines are connected from the MAC to a single PHY. The reason for multiple addresses for MDIO is for SOCs that contain multiple MAC modules and for switch chips. The MII from each MAC module connect to its PHY. However, to save pins on the SOC, there will be only one set of MDIO pins. The MACs will share these lines communicating with ...

4

Figure 3-4 shows an oscillator, not a crystal. Similarly, the datasheet says "RMII - 50 MHZ CLOCK MODE [...] An external 50 MHz clock source (oscillator) connected to XI" A "crystal" would be excited by XO and the desired clock frequency would come into XI. In this context, an "oscillator" is something which excites itself externally, and just provides a ...

3

MII MAC Mode This mode will be used when you want to connect MAC(Media Access Control) Devices which have inbuilt Ethernet Interface Control like Processor(say iMX28), Controller(say AT91SAM).These are capable to taking the data for processing and using it for different purposes.Other case is cascading i.e. connecting two or more KSZ8863RL together for ...

3

For example, using a twisted pair, the formula that determines characteristic impedance, Z0 is: - $Z_0 = \dfrac{120}{\sqrt{\epsilon_r}}\cdot ln(\dfrac{2S}{D})$ If permittivity ($\epsilon_r$) is held constant at 4 then you will find that you have to get a a very large "S" distance before the impedance is in the kohm range. For D = 0.5mm, an S value of ...

3

Good questions. 1) Does REF_CLK must be routed without vias. Whenever you see something like "must be routed without vias" without a good explanation, chances are that someone does not fully understand what is going on and just think that is a good idea. One of several things may be the issue: Different trace impedance on different layers, which will ...

3

"PECL compatible" doesn't mean the part actually has a PECL topology in the output driver circuit, it just means it can be used with PECL parts. In fact Fig 9 of the DP83620 datasheet strongly implies the DP83620 outputs are not PECL because true PECL would require a pull-down resistor on the output in order to function at all. Since the DP83620 datasheet ...

3

If you have to use separate magnetics then you could use the same basic spacing and trace widths from the magnetics and over to the RJ45 as you used for the Diff Pair coming from the PHY. Do keep the jack end of the magnetics component as close to the RJ45 as possible. Note that if you were to use a MagJack (which is an RJ45 with the magnetics built in may ...

3

This question isn't framed (hah, pun) quite right. Start of frame detection isn't an alternative to PTP, but rather an augmentation of it. In a PTP implementation, you must choose how you actually timestamp the ingressing/egressing packets. A trivial method to do this is software timestamping, wherein your PTP implementation fetches current system time and ...

3

If the PHY has a crystal driver built in, then using a separate oscillator just for the PHY is rather silly. A crystal with caps is usually cheaper, smaller, and takes less power than a whole separate crystal oscillator module.

3

Find a switch/PHY chip that has dual (R)MII interfaces. For example: http://www.farnell.com/datasheets/2175960.pdf. One MII to the compute module, the second RMII to the microcontroller and you have 2 ports left that you can connect to regular magnetics and bring outside.

3

Using exactly the same values as you did, but with another calculator (from EEWeb), I get: Which is different from what you had, and closer to the target. There are several models that can be used to estimate the differential impedance, and different tools may use different underlying computation techniques, so you can get different results. In any case, ...

3

On a hardware level: The CAN bus works by a voltage differential between a pair of lines. The Ethernet bus is current-driven and is coupled through transformers at both ends, providing galvanic insulation and avoiding any grounding issue. The electrical operation principle is very different between these buses. Ethernet bus is by default galvanically ...

2

The UI would be the inverse of the baud rate on the serial side of the serializer/deserializer blocks. In other words, 1/10.3125 Gbps, or 97 ps.

2

The IC you mentioned (Vitesse VSC8221) is a typical 10/100/1000BASE-T/TX/T PHY with a 1000BASE-X/SGMII interface to the MAC. It is intended to design SFP modules, not to design media converters. As i see you try to design a converter for 10/100/1000 Mbps copper to/from 1000 Mbps fiber optic. If it is so, you should use a switch instead of simple PHYs, ...

2

MDI is a type of Ethernet port connection using twisted pair cabling. The MDI is the component of the media attachment unit that provides the physical and electrical connection to the cabling medium which is used to connect network devices (hubs and switches) with other hubs and switches without the use of a crossover cable or null modem. Where MII is Media ...

2

The best way to see the difference is to view this chart in the Microchip TCP/IP Stack Help. I cannot say where this is in the newer versions of the MAL, but in v2012-10-15, it can be found in C:\Microchip Solutions v2012-10-15\Microchip\Help\TCPIP Stack Help.chm. There is a nice chart under Release Notes->Stack Performance. The MAL can be found here, ...

2

As far as I know there are no 32-bit versions of the PIC18F97J60 chip. I believe Luminary Micro (now TI) did have one, but I am not sure if they are still available (I think I read somewhere they went EOL). The ENC424J600/624J600 chips provide MAC+PHY in 1 chip, and communicate via SPI or parallel interface to any microcontroller. However you need to haul ...

2

Many older Ethernet PHYs do not support auto-mdix. Therefore the first thing I would try is changing the cable. If your current cable is straight through try a crossover, if your current cable is crossover try a straight through cable. If that doesn't help then I would try looking at what speed and duplex mode they negotiate with the PC. In particular is ...

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