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41

The PLL lets you be flexible with clock speed even after you've built the board, and of course, it lets you generate many different frequencies from the one onboard oscillator. Honestly, just having a PLL so you can generate many frequencies off the onboard RC oscillator makes it worth having a PLL. That way you can operate flexibly with no external ...


32

RF comms do not transmit one bit of information per cycle of the carrier wave - that would be digital baseband communications and it requires incredible amounts of bandwidth. Incidentally, you can buy FPGAs with built-in 28 Gbps serdes hard blocks. These can serialize and deserialize data for 100G ethernet (4x25G + coding overhead). I suppose the '...


23

This is done using a device called a phase-locked loop, or PLL. Here is a block diagram of a basic PLL: simulate this circuit – Schematic created using CircuitLab The oscillator on the motherboard does not run at the CPU clock frequency, instead it runs at a frequency on the order of 100 MHz. This oscillator serves only as a known, stable reference ...


23

Some extra descriptions of the other use cases/modes may help. • Zero-delay buffer A zero-delay buffer is where the phase of the output clock and the phase of the input clock are identical. By using a feedback network it is possible to make a synthesized output clock (e.g. to an IO pin) match exactly with the phase of an input clock pin. This is useful for ...


17

What you need is a PLL, a phase-locked loop. It works by comparing one oscillator that you can control, with a reference oscillator. The trick is that it is easy to divide the frequency of an oscillator using a digital counter, so what you do here is to divide the 14.3 MHz oscillator by 143, the 10.0 MHz reference by 100, and then use the output from this ...


13

You could do a 3:1 gear ratio and do the divisor at 32768. 32768 = 10,923 + 10,923 + 10,922 which indicates a state machine that first counts to 10,923 repeats and then drops a count, it would be accurate every 3 seconds. The worst absolute error you would see is 31 PPM which is about what the crystal can do (depending on your crystal).


13

There are several reasons for this. A phase locked loop, or PLL, is a circuit that is used to generate a stable frequency that has a specific mathematical relationship to some reference frequency. Specifically, it is a circuit that is used to control some sort of electrically tunable oscillator (usually a voltage controlled oscillator, or VCO) so that its ...


12

Deeper interpretation: The PLL is actually producing clock cycles during that whole time. The problem is that until it achieves "lock", the clock cycles may at times be too short to allow the CPU to operate correctly, as the VCO control voltage swings both above and below the target value before settling down. So what this specification is really telling ...


11

Take the 32,768 Hz square wave and feed it through a 98 kHz band pass filter to leave (mainly) its 3rd harmonic - this is fairly trivial. Now you have 3 times 32,768 Hz which you can divide with the previous circuit you used to get 3 Hz.


9

Yes, a square wave can be fine. When you mix, you get the sum and the difference of the frequency components from each input. The square wave consists of the fundamental and all the odd harmonics, so you need to do some filtering somewhere, of course. The Softrock Ensamble RXTX is a simple direct conversion HF transceiver which makes a good example. There's ...


9

You can't. You can get any rational multiple of the input frequency, because at intervals of some finite period the output and input will be exactly in phase with each other. With an irrational number, they can be in phase at exactly one point ever. Why do you want this anyway?


8

Yes. You can build a synthesiser to generate a frequency of sqrt(2). Can you write down an irrational number like sqrt(2), as a decimal fraction? Is it possible, even in principle? No. But you can approximate an irrational number, as closely as you like, with a rational fraction. You can choose an error level, and write down a number that gets within that....


8

Is it the case that one node will communicate using 2405 MHz and the other 2405 MHz + 10 ppm? Yes, one will transmit at 2405 MHz and the other will use 2405.02405 MHz plus there will be jitter caused by the PLL (in both systems) and this may be in the region of +/- 100 ppm at a variable frequency in the hundreds of Hz to low kHz range (with some ...


8

Been there, done that. Apart from other reasons mentioned here is a different one: The marketing guys want to make the chip design as cheap as possible. Thus they prefer to use cheap crystals. The ones use for Ethernet fall in that category. So you often end up having to use a 25MHz crystal. At the same time marketing want powerful processors. Thus the ...


8

I don't understand how PLL relates to microcontroller. I'm not sensing any phase shift or trying to stabilize any signal here, and I don't get how the PLL magically produce a 400MHz clock. From the point of view of a microcontroller, a PLL is just a frequency multiplier. It takes some reference frequency like from a 10 MHz oscillator and generates all the ...


8

The "Good News" first: I can save you using an online calculator. "ppm" is for "parts per million"; so 50 ppm simply means a relative error of 50·10⁻⁶; at 200 MHz, that means 200·10⁶ Hz · 50·10⁻⁶ = 10000 Hz. It's that simple! Bad news: Doesn't have anything to do with jitter. Your clock could be running at, say 200.010 MHz (...


7

Recovering a clock from an intermittent stream of pulses is a non-trivial design exercise. I generally try to center the edge of the clock on the pulses, then the clock edge can be used to capture the presence/absence of the pulse in a flip-flop. A hybrid digital/analog circuit demonstrates the concept more clearly: simulate this circuit – Schematic ...


7

It is true that 32768 Hz does not divide by 3 Hz, but it is not off by much. You need a solution which appears visually smooth and is accurate on average over time. Simply create logic which: Counts 10923 input clocks and takes a step Counts 10923 input clocks and takes a step Counts 10922 input clocks and takes a step and repeats. You would need ...


7

Here's my attempt at a layman summary, adapted from this answer. When we talk about communication happening "at 24 GHz", we're referring to a small range of frequencies. In order for the signal "at 24 GHz" not to trample all over the signals at all the other frequencies, there's a hard limit on how much the signal is allowed to differ from a 24 GHz sinewave....


7

It seems to me the accepted answer (by Sparky256) views the PLL simply as a filter and completely ignores its actual purpose, which is being a control system, controlling the phase of a signal. The order of a control system signifies its number of internal states. In a system that has a single input, the states beyond the first state (order) are equivalent ...


7

In addition to previous answers... Your STM micro almost certainly has the second oscillator for the real-time clock. This lets the clock keep running (consuming minimal power) whilst the rest of the chip and the rest of the circuit is powered down. The device can then keep its clock and calendar running, and typically it can also restart the main processor ...


7

As frequency is the rate at which phase changes, locking the phase automatically implies locking the frequency. To state that a PLL locks frequency as well is unnecessary. The converse is not true, a locked frequency does not imply a consistent phase.


7

Directly from the reference manual, pay attention to the last line. Without oscilloscope you can use TIM5 to perform a comparison between two clocks. Since TIM5 can input capture from LSI or LSE, you can compare the SYSCLK (the one TIM5 is running on) with any of those. TIM11 can do HSE. Which is described in detail in chapter: 6.2.11 Internal/external ...


7

To add to the other answers, there are couple of other reasons why a PLL may be useful: To reduce EMC emissions (while also saving money, and reducing the chance of glitches) To quote from ST application note AN1709: Some microcontrollers have an embedded programmable PLL Clock Generator allowing the usage of standard 3 to 25 MHz crystals to obtain a large ...


7

The problem is the 1x probe mode. It does not have enough bandwidth in 1x mode. Set it to 10x for more bandwidth. Always use 10x probes, unless you know you must use 1x mode, and that does not happen very often.


6

There is much out there on the basic descripton of a phase-locked loop (PLL). Basically, a PLL is a phase comparator producing a feedback signal to adjust a independent oscillator to exactly match the frequency of some incoming signal. The output of the oscillator then is a locally produced copy of the incoming signal. That by itself may not sound useful, ...


6

To answer your question, the same guidelines do not apply to ASICs and gated clocks are used very often to reduce power consumption. In FPGAs, clock signals have dedicated routing resources that ensure low skew delivery of the clocks to fairly large areas of circuitry. If you try to gate the clock then the output of the gate will probably be forced to use ...


6

Your second implementation fails because of what is a common mistake. The code pattern: if rising_edge(clk_a) then signal_a <= '1'; elsif falling_edge(clk_b) then signal_a <= '0'; end if; Cannot be realised in hardware, because it describes a 1-bit register with two different clock inputs. Such a register does not exist in the FPGA fabric; ...


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