# Tag Info

31

RF comms do not transmit one bit of information per cycle of the carrier wave - that would be digital baseband communications and it requires incredible amounts of bandwidth. Incidentally, you can buy FPGAs with built-in 28 Gbps serdes hard blocks. These can serialize and deserialize data for 100G ethernet (4x25G + coding overhead). I suppose the '...

21

This is done using a device called a phase-locked loop, or PLL. Here is a block diagram of a basic PLL: simulate this circuit – Schematic created using CircuitLab The oscillator on the motherboard does not run at the CPU clock frequency, instead it runs at a frequency on the order of 100 MHz. This oscillator serves only as a known, stable reference ...

18

In most cases, the best way to tell if the frequency of the feedback waveform precisely matches the frequency of reference waveform is to observe whether the two waveforms maintain a fixed phase relationship. If the frequency of the feedback waveform is slightly higher than that of the reference wave, its phase will to lead that of the reference wave form ...

17

What you need is a PLL, a phase-locked loop. It works by comparing one oscillator that you can control, with a reference oscillator. The trick is that it is easy to divide the frequency of an oscillator using a digital counter, so what you do here is to divide the 14.3 MHz oscillator by 143, the 10.0 MHz reference by 100, and then use the output from this ...

14

A PLL controls a voltage-controlled oscillator in order to bring its frequency (or some derivative of it) into phase (and frequency) lock with a reference signal. PLLs have many applications, from creating a "clean" replica of a noisy reference signal (with amplitude and phase variations removed), to creating new frequencies through multiplication and ...

13

You could do a 3:1 gear ratio and do the divisor at 32768. 32768 = 10,923 + 10,923 + 10,922 which indicates a state machine that first counts to 10,923 repeats and then drops a count, it would be accurate every 3 seconds. The worst absolute error you would see is 31 PPM which is about what the crystal can do (depending on your crystal).

12

Deeper interpretation: The PLL is actually producing clock cycles during that whole time. The problem is that until it achieves "lock", the clock cycles may at times be too short to allow the CPU to operate correctly, as the VCO control voltage swings both above and below the target value before settling down. So what this specification is really telling ...

12

There are several reasons for this. A phase locked loop, or PLL, is a circuit that is used to generate a stable frequency that has a specific mathematical relationship to some reference frequency. Specifically, it is a circuit that is used to control some sort of electrically tunable oscillator (usually a voltage controlled oscillator, or VCO) so that its ...

11

From a more theoretical angle, frequency is the time derivative of phase. Equivalently, phase is the time integral of frequency. So, when a phase detector is used to control frequency via a VCO, there is an integration around the loop. Or, roughly speaking, a low-pass filtering effect. As supercat points out, the advantage gained is the rejection of "...

11

Take the 32,768 Hz square wave and feed it through a 98 kHz band pass filter to leave (mainly) its 3rd harmonic - this is fairly trivial. Now you have 3 times 32,768 Hz which you can divide with the previous circuit you used to get 3 Hz.

9

The normal method for using PLL to multiply frequency is analogous to the normal method of using an op-amp to multiply the voltage of a high-impedance signal: the non-inverting input is fed the input signal directly; the inverting input is fed a scaled-down version of the output. The op amp will vary its output voltage as necessary to make the two inputs ...

9

Yes, a square wave can be fine. When you mix, you get the sum and the difference of the frequency components from each input. The square wave consists of the fundamental and all the odd harmonics, so you need to do some filtering somewhere, of course. The Softrock Ensamble RXTX is a simple direct conversion HF transceiver which makes a good example. There's ...

9

You can't. You can get any rational multiple of the input frequency, because at intervals of some finite period the output and input will be exactly in phase with each other. With an irrational number, they can be in phase at exactly one point ever. Why do you want this anyway?

8

Yes. You can build a synthesiser to generate a frequency of sqrt(2). Can you write down an irrational number like sqrt(2), as a decimal fraction? Is it possible, even in principle? No. But you can approximate an irrational number, as closely as you like, with a rational fraction. You can choose an error level, and write down a number that gets within that....

8

Is it the case that one node will communicate using 2405 MHz and the other 2405 MHz + 10 ppm? Yes, one will transmit at 2405 MHz and the other will use 2405.02405 MHz plus there will be jitter caused by the PLL (in both systems) and this may be in the region of +/- 100 ppm at a variable frequency in the hundreds of Hz to low kHz range (with some ...

8

Been there, done that. Apart from other reasons mentioned here is a different one: The marketing guys want to make the chip design as cheap as possible. Thus they prefer to use cheap crystals. The ones use for Ethernet fall in that category. So you often end up having to use a 25MHz crystal. At the same time marketing want powerful processors. Thus the ...

7

It is true that 32768 Hz does not divide by 3 Hz, but it is not off by much. You need a solution which appears visually smooth and is accurate on average over time. Simply create logic which: Counts 10923 input clocks and takes a step Counts 10923 input clocks and takes a step Counts 10922 input clocks and takes a step and repeats. You would need ...

7

I found this link to an amazing document that spells out the fine details up to 4th order filters. Filter order just refers to the number of poles used to filter the output of the phase comparator so it provides a smooth DC error voltage to the VCO. 1st order filters are actually just the VCO's filter characteristics, requiring a minimum amount of time to ...

7

In addition to previous answers... Your STM micro almost certainly has the second oscillator for the real-time clock. This lets the clock keep running (consuming minimal power) whilst the rest of the chip and the rest of the circuit is powered down. The device can then keep its clock and calendar running, and typically it can also restart the main processor ...

6

To produce such a signal one way would be to use an arbitrary voltage source: Syntax: Bnnn n001 n002 V = [expression] This is a source with a function you define. Here is an example of sweeping from 1 to 20Hz in LTSpice: And the simulation: I have used the time variable (defined in LTSpice as current sim time) to change the frequency (the (19 * time) part ...

6

There is much out there on the basic descripton of a phase-locked loop (PLL). Basically, a PLL is a phase comparator producing a feedback signal to adjust a independent oscillator to exactly match the frequency of some incoming signal. The output of the oscillator then is a locally produced copy of the incoming signal. That by itself may not sound useful, ...

6

Recovering a clock from an intermittent stream of pulses is a non-trivial design exercise. I generally try to center the edge of the clock on the pulses, then the clock edge can be used to capture the presence/absence of the pulse in a flip-flop. A hybrid digital/analog circuit demonstrates the concept more clearly: simulate this circuit – Schematic ...

6

Here's my attempt at a layman summary, adapted from this answer. When we talk about communication happening "at 24 GHz", we're referring to a small range of frequencies. In order for the signal "at 24 GHz" not to trample all over the signals at all the other frequencies, there's a hard limit on how much the signal is allowed to differ from a 24 GHz sinewave....

6

Your second implementation fails because of what is a common mistake. The code pattern: if rising_edge(clk_a) then signal_a <= '1'; elsif falling_edge(clk_b) then signal_a <= '0'; end if; Cannot be realised in hardware, because it describes a 1-bit register with two different clock inputs. Such a register does not exist in the FPGA fabric; ...

6

It seems to me the accepted answer (by Sparky256) views the PLL simply as a filter and completely ignores its actual purpose, which is being a control system, controlling the phase of a signal. The order of a control system signifies its number of internal states. In a system that has a single input, the states beyond the first state (order) are equivalent ...

6

how the output frequency tracks the input say for a step change in input frequency If you look at the control voltage into the VCO, its average value (ignoring ripple) is representative of the output frequency produced: - If this filtered control voltage is stable (not end stopped) then the PLL is in equilibrium or has settled to a constant steady state ...

6

The PLL is sensitive to noise on its power input pin in a way that the core really is not (The PLL is essentially analogue at least as far as the VCO and squarer are concerned, so ANY noise will impact the performance), the core just needs the supply to stay within an acceptable range. The 10uH and caps form a filter to massively reduce the high frequency ...

6

PLLs can be used to multiply and divide frequencies. CPUs that have PLLs to generate their clocks are highly reconfigurable. The clock speed can be varied relative to the external reference clock over a wide range, and it's the PLL that makes this possible.

6

PLLs are used primarily to generate one or more faster or slower clocks from a reference clock. You might have say a fixed 100MHz crystal, but then want to run your CPU at 2GHz, so a PLL is required to increase the frequency (a 2GHz clock crystal isn't feasible). Additional you may want to be able to change your CPU frequency on the fly (e.g. a turbo clock)...

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