44
votes
Accepted
What is the purpose of PLL in a general microcontroller
The PLL lets you be flexible with clock speed even after you've built the board, and of course, it lets you generate many different frequencies from the one onboard oscillator.
Honestly, just having a ...
- 54.4k
25
votes
Why is the MCU clock out waveform sinusoidal and not square pulse
It's hard to see (or even generate) a 170 MHz ideal square wave.
Use the 10:1 attenuation mode.
In the 24 MHz case, you probably don't have a good ground connection on your scope probe -- you need a ...
- 18.2k
24
votes
Accepted
Using PLLs inside FPGAs
Some extra descriptions of the other use cases/modes may help.
• Zero-delay buffer
A zero-delay buffer is where the phase of the output clock and the phase of the input clock are identical. By using ...
- 62k
23
votes
Accepted
How do processors control their clock speed?
This is done using a device called a phase-locked loop, or PLL. Here is a block diagram of a basic PLL:
simulate this circuit – Schematic created using CircuitLab
The oscillator on the ...
- 40.6k
21
votes
Why do we need phase-locked loops?
PLLs provide a number of features that the direct connection doesn't. A few examples:
With proper filtering in the loop filter, they can provide a more stable clock by attenuating jitter
When a self ...
- 17k
18
votes
Accepted
How do I drive 14.3Mhz clock input from 10MHz?
What you need is a PLL, a phase-locked loop. It works by comparing one oscillator that you can control, with a reference oscillator. The trick is that it is easy to divide the frequency of an ...
- 13.4k
13
votes
Accepted
Why is there a PLL in CPU?
There are several reasons for this. A phase locked loop, or PLL, is a circuit that is used to generate a stable frequency that has a specific mathematical relationship to some reference frequency. ...
- 40.6k
13
votes
Why do we need phase-locked loops?
One of the main uses of a PLL is basically an opamp for clocks, with input/output in frequency instead of voltage. You put a transfer function in the feedback (for example a divider) and you get the ...
- 69k
12
votes
Accepted
Why microcontroller takes many clock cycles to start up with PLL clock source?
Deeper interpretation: The PLL is actually producing clock cycles during that whole time. The problem is that until it achieves "lock", the clock cycles may at times be too short to allow the CPU to ...
- 167k
11
votes
Why do we need phase-locked loops?
In the example shown, the PLL is used for FM demodulation. To do this the VCO tracks the incoming Ref input. If the input frequency increases, the voltage to the VCO must increase in order for the VCO ...
- 5,862
9
votes
Accepted
How do I use a PLL to multiply the input frequency by an irrational number?
You can't.
You can get any rational multiple of the input frequency, because at intervals of some finite period the output and input will be exactly in phase with each other. With an irrational ...
- 46.3k
9
votes
Ways to observe clock signal of an STM32 MCU
Directly from the reference manual, pay attention to the last line.
Without oscilloscope you can use TIM5 to perform a comparison between two clocks.
Since TIM5 can input capture from LSI or LSE, you ...
- 21.7k
8
votes
How do I use a PLL to multiply the input frequency by an irrational number?
Yes. You can build a synthesiser to generate a frequency of sqrt(2).
Can you write down an irrational number like sqrt(2), as a decimal fraction? Is it possible, even in principle? No.
But you can ...
- 155k
8
votes
Accepted
What is the difference between first order, second order and third order phase locked loops?
It seems to me the accepted answer (by Sparky256) views the PLL simply as a filter and completely ignores its actual purpose, which is being a control system, controlling the phase of a signal.
The ...
- 342
8
votes
Accepted
MCU clock drift and radio frequency drift - are they the same?
Is it the case that one node will communicate using 2405 MHz and the
other 2405 MHz + 10 ppm?
Yes, one will transmit at 2405 MHz and the other will use 2405.02405 MHz plus there will be jitter ...
- 426k
8
votes
Why is there a PLL in CPU?
Been there, done that.
Apart from other reasons mentioned here is a different one:
The marketing guys want to make the chip design as cheap as possible. Thus they prefer to use cheap crystals. The ...
- 14.2k
8
votes
What is the purpose of PLL in a general microcontroller
I don't understand how PLL relates to microcontroller. I'm not sensing any phase shift or trying to stabilize any signal here, and I don't get how the PLL magically produce a 400MHz clock.
From the ...
- 13.8k
8
votes
Accepted
Clock jitter - ppm, ui, ps
The "Good News" first: I can save you using an online calculator.
"ppm" is for "parts per million"; so 50 ppm simply means a relative error of 50·10⁻⁶; at 200 MHz, that ...
- 85.7k
8
votes
Meaning of "three-stating" a PLL charge pump
The more common word is "tristate" (as an adjective or verb), not "three-state". In context, it means to make a pin high-impedance, neither driving high nor low — see "...
- 6,275
7
votes
How do processors control their clock speed?
In addition to previous answers...
Your STM micro almost certainly has the second oscillator for the real-time clock. This lets the clock keep running (consuming minimal power) whilst the rest of the ...
- 6,020
7
votes
Definition of Phase Locked Loop
As frequency is the rate at which phase changes, locking the phase automatically implies locking the frequency. To state that a PLL locks frequency as well is unnecessary.
The converse is not true, a ...
- 155k
7
votes
What is the purpose of PLL in a general microcontroller
To add to the other answers, there are couple of other reasons why a PLL may be useful:
To reduce EMC emissions (while also saving money, and reducing the chance of glitches)
To quote from ST ...
- 734
7
votes
Accepted
Issue for TCXO through frequency multiplier (PLL) for STM32 I2S signal
The problem is the 1x probe mode.
It does not have enough bandwidth in 1x mode.
Set it to 10x for more bandwidth.
Always use 10x probes, unless you know you must use 1x mode, and that does not happen ...
- 119k
7
votes
Problems increasing VCO frequency above datasheet recommendations
Well, 720 MHz is 66% over the 432 MHz limit so highly unlikely it will work.
As you have correctly calculated, you can achieve 168 MHz as the highest core clock when 48 MHz USB clock is required. That ...
- 119k
6
votes
Accepted
Pulse on edge of different clock
Your second implementation fails because of what is a common mistake. The code pattern:
...
- 1,977
6
votes
Accepted
How do I observe a PLL's frequency tracking once the lock has been acquired?
how the output frequency tracks the input say for a step change in
input frequency
If you look at the control voltage into the VCO, its average value (ignoring ripple) is representative of the output ...
- 426k
6
votes
Accepted
PLL power supply filtering
The PLL is sensitive to noise on its power input pin in a way that the core really is not (The PLL is essentially analogue at least as far as the VCO and squarer are concerned, so ANY noise will ...
- 17k
6
votes
Stability of a PLL
The CLTF can be unstable, it depends on the ratio of time constants. It's easier than you think to make a stable loop, and with minimal mathematics, and no Laplace functions.
First of all, short ...
- 155k
6
votes
Why is there a PLL in CPU?
PLLs can be used to multiply and divide frequencies. CPUs that have PLLs to generate their clocks are highly reconfigurable. The clock speed can be varied relative to the external reference clock over ...
- 167k
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