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48 votes
Accepted

What is the purpose of PLL in a general microcontroller

The PLL lets you be flexible with clock speed even after you've built the board, and of course, it lets you generate many different frequencies from the one onboard oscillator. Honestly, just having a ...
DKNguyen's user avatar
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25 votes

Why is the MCU clock out waveform sinusoidal and not square pulse

It's hard to see (or even generate) a 170 MHz ideal square wave. Use the 10:1 attenuation mode. In the 24 MHz case, you probably don't have a good ground connection on your scope probe -- you need a ...
jp314's user avatar
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24 votes
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Using PLLs inside FPGAs

Some extra descriptions of the other use cases/modes may help. • Zero-delay buffer A zero-delay buffer is where the phase of the output clock and the phase of the input clock are identical. By using ...
Tom Carpenter's user avatar
23 votes
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How do processors control their clock speed?

This is done using a device called a phase-locked loop, or PLL. Here is a block diagram of a basic PLL: simulate this circuit – Schematic created using CircuitLab The oscillator on the ...
alex.forencich's user avatar
22 votes

Why do we need phase-locked loops?

PLLs provide a number of features that the direct connection doesn't. A few examples: With proper filtering in the loop filter, they can provide a more stable clock by attenuating jitter When a self ...
nanofarad's user avatar
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13 votes
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Why is there a PLL in CPU?

There are several reasons for this. A phase locked loop, or PLL, is a circuit that is used to generate a stable frequency that has a specific mathematical relationship to some reference frequency. ...
alex.forencich's user avatar
13 votes

Why do we need phase-locked loops?

One of the main uses of a PLL is basically an opamp for clocks, with input/output in frequency instead of voltage. You put a transfer function in the feedback (for example a divider) and you get the ...
bobflux's user avatar
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12 votes
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Why microcontroller takes many clock cycles to start up with PLL clock source?

Deeper interpretation: The PLL is actually producing clock cycles during that whole time. The problem is that until it achieves "lock", the clock cycles may at times be too short to allow the CPU to ...
Dave Tweed's user avatar
  • 175k
12 votes

Why do we need phase-locked loops?

In the example shown, the PLL is used for FM demodulation. To do this the VCO tracks the incoming Ref input. If the input frequency increases, the voltage to the VCO must increase in order for the VCO ...
Kartman's user avatar
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10 votes
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What is the difference between first order, second order and third order phase locked loops?

It seems to me the accepted answer (by Sparky256) views the PLL simply as a filter and completely ignores its actual purpose, which is being a control system, controlling the phase of a signal. The ...
Sagie's user avatar
  • 362
9 votes

Ways to observe clock signal of an STM32 MCU

Directly from the reference manual, pay attention to the last line. Without oscilloscope you can use TIM5 to perform a comparison between two clocks. Since TIM5 can input capture from LSI or LSE, you ...
Jeroen3's user avatar
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9 votes
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Clock jitter - ppm, ui, ps

The "Good News" first: I can save you using an online calculator. "ppm" is for "parts per million"; so 50 ppm simply means a relative error of 50·10⁻⁶; at 200 MHz, that ...
Marcus Müller's user avatar
8 votes
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MCU clock drift and radio frequency drift - are they the same?

Is it the case that one node will communicate using 2405 MHz and the other 2405 MHz + 10 ppm? Yes, one will transmit at 2405 MHz and the other will use 2405.02405 MHz plus there will be jitter ...
Andy aka's user avatar
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8 votes

Why is there a PLL in CPU?

Been there, done that. Apart from other reasons mentioned here is a different one: The marketing guys want to make the chip design as cheap as possible. Thus they prefer to use cheap crystals. The ...
Oldfart's user avatar
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8 votes

What is the purpose of PLL in a general microcontroller

I don't understand how PLL relates to microcontroller. I'm not sensing any phase shift or trying to stabilize any signal here, and I don't get how the PLL magically produce a 400MHz clock. From the ...
user1850479's user avatar
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8 votes

Meaning of "three-stating" a PLL charge pump

The more common word is "tristate" (as an adjective or verb), not "three-state". In context, it means to make a pin high-impedance, neither driving high nor low — see "...
hobbs's user avatar
  • 7,637
7 votes

How do processors control their clock speed?

In addition to previous answers... Your STM micro almost certainly has the second oscillator for the real-time clock. This lets the clock keep running (consuming minimal power) whilst the rest of the ...
Graham's user avatar
  • 6,200
7 votes

Definition of Phase Locked Loop

As frequency is the rate at which phase changes, locking the phase automatically implies locking the frequency. To state that a PLL locks frequency as well is unnecessary. The converse is not true, a ...
Neil_UK's user avatar
  • 169k
7 votes

What is the purpose of PLL in a general microcontroller

To add to the other answers, there are couple of other reasons why a PLL may be useful: To reduce EMC emissions (while also saving money, and reducing the chance of glitches) To quote from ST ...
Steve Melnikoff's user avatar
7 votes
Accepted

Issue for TCXO through frequency multiplier (PLL) for STM32 I2S signal

The problem is the 1x probe mode. It does not have enough bandwidth in 1x mode. Set it to 10x for more bandwidth. Always use 10x probes, unless you know you must use 1x mode, and that does not happen ...
Justme's user avatar
  • 158k
7 votes

Problems increasing VCO frequency above datasheet recommendations

Well, 720 MHz is 66% over the 432 MHz limit so highly unlikely it will work. As you have correctly calculated, you can achieve 168 MHz as the highest core clock when 48 MHz USB clock is required. That ...
Justme's user avatar
  • 158k
6 votes
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How do I observe a PLL's frequency tracking once the lock has been acquired?

how the output frequency tracks the input say for a step change in input frequency If you look at the control voltage into the VCO, its average value (ignoring ripple) is representative of the output ...
Andy aka's user avatar
  • 465k
6 votes
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PLL power supply filtering

The PLL is sensitive to noise on its power input pin in a way that the core really is not (The PLL is essentially analogue at least as far as the VCO and squarer are concerned, so ANY noise will ...
Dan Mills's user avatar
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6 votes

Stability of a PLL

The CLTF can be unstable, it depends on the ratio of time constants. It's easier than you think to make a stable loop, and with minimal mathematics, and no Laplace functions. First of all, short ...
Neil_UK's user avatar
  • 169k
6 votes

Why is there a PLL in CPU?

PLLs can be used to multiply and divide frequencies. CPUs that have PLLs to generate their clocks are highly reconfigurable. The clock speed can be varied relative to the external reference clock over ...
Dave Tweed's user avatar
  • 175k
6 votes

Why is there a PLL in CPU?

PLLs are used primarily to generate one or more faster or slower clocks from a reference clock. You might have say a fixed 100MHz crystal, but then want to run your CPU at 2GHz, so a PLL is required ...
Tom Carpenter's user avatar
6 votes

What is the difference between a PLL and a frequency-synthesizer?

According to Wikipedia a frequency synthesizer is an electronic circuit that generates a range of frequencies from a single reference frequency. A block schematic could look like: And I see a ...
Bimpelrekkie's user avatar
6 votes
Accepted

Is it possible to create a PLL purely in digital design, if so how?

This is definitely possible. It is called an all digital PLL. Instead of a VCO, you use a numerically controlled oscillator, or NCO. An NCO is basically just a counter, called a phase accumulator, ...
alex.forencich's user avatar
6 votes

Ways to observe clock signal of an STM32 MCU

Some ideas Configure SysTick timer to tick after 1680000 clocks (10ms) and toggle a LED/GPIO each 100 interrupts to get 1s update rate (the signal will have frequency of 0.5Hz). The interrupt and SW ...
akwky's user avatar
  • 1,594

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