New answers tagged pll
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Are two FPLLs in sync?
Two FPLLs are being driven by a common clock and the output of each FPLL is used to drive a counter after achieving a lock. When we turn on the circuit both FPLLs miraculously lock EXACTLY at the same ...
- 159k
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Debugging PLL STW81200TR not locking
The recommended clock configuration for a single ended input (A), shows an AC coupling capacitor in series on the REF_CLKP pin, allowing the DC bias to be set internally to the PLL. In your schematic ...
- 3,877
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Debugging PLL STW81200TR not locking
Did you see this ?
I don't see the square kind of clock but more sinusoidal clock of 100 MHz ...
For a signal of 100 MHz, a scope as the "sds1202x-e" should be a little "short" ...
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