New answers tagged

1 vote

Are two FPLLs in sync?

Two FPLLs are being driven by a common clock and the output of each FPLL is used to drive a counter after achieving a lock. When we turn on the circuit both FPLLs miraculously lock EXACTLY at the same ...
Neil_UK's user avatar
  • 159k
0 votes

Debugging PLL STW81200TR not locking

The recommended clock configuration for a single ended input (A), shows an AC coupling capacitor in series on the REF_CLKP pin, allowing the DC bias to be set internally to the PLL. In your schematic ...
colintd's user avatar
  • 3,877
0 votes

Debugging PLL STW81200TR not locking

Did you see this ? I don't see the square kind of clock but more sinusoidal clock of 100 MHz ... For a signal of 100 MHz, a scope as the "sds1202x-e" should be a little "short" ...
Antonio51's user avatar
  • 11.3k

Top 50 recent answers are included