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29

In a word: Efficiency. You can use a PMOS transistor to drive a logic output high (e.g. VDD) when the input is low (e.g. GND). However, you can't use that same PMOS transistor to drive a logic output low when the input is high. When you drive the input high in your PMOS inverter, it turns off, leaving the output effectively high-impedance, which is not ...


14

That is the body connection. All MOSFETs have a fourth connection to the substrate, but for discrete MOSFETs this is normally connected internally to the source which results in a parasitic body diode anti-parallel to the source-drain. So in a typical discrete MOSFET you see the body connection tied to the source terminal and you get the MOSFET symbol which ...


12

a better idea for this, if you want to use a PMOS high side switch, would be to have the ATSAMD21 switch a low-side NPN switch, which then switches the PMOS for the SIM530. Example: simulate this circuit – Schematic created using CircuitLab R2 (arbitrarily chosen to be 50x R1) pulls Q1 to ground (off) if D1 is in high impedance state, which it may be ...


11

I'm assuming the type of circuit you are thinking of is this: - For use on your battery powered circuit I see little to say against it. A couple of things though; you need to pick a FET with low \$V_{GS(threshold)}\$ so that the device is still offering a tiny volt drop at low battery voltages AND you'll need a FET with low \$R_{DS(on)}\$ so that at 30mA (...


11

That is called a complementary transistor. BS250 is complementary to 2N7000. Check this list for PFETs with the characteristics you want. However I don't know what popular transistors you'll find there.


10

If all the components are identical, or 'symmetrical', this is because for the PMOS the load is connected on the source. The drain current of a MOS transistor is a function of its gate to source voltage, while drain voltage has little effect to it. In the case of the NMOS you are driving the transistor with 3.3V to turn it on, since the source is always ...


9

The P-Channel MOSFET needs to switch up to 20V. And that's the catch, when making the MCU output high impedance, you could have 20 V at that MCU's output. You would be violating the maximum ratings of the MCU. But actually you would not get to 20 V at that output as the ESD protection diodes in the MCU will pull down that voltage (to roughly Vdd + one ...


8

ZVP3306A is not too bad a choice as a complimentary part to the 2N7000, rather cheaper (~30%) than the BS250, but it is still more than six times more expensive than the surface mount SOT-23 BSS84. The 2N7000 is not good for 500mA, so you're not really looking for the equivalent (and you'll probably be pushed out of a TO-92 package into a TO-220 such as the ...


8

CMOS, while more complex to make, consumes very little power when not switching, while PMOS consumes more power even when it's not switching. From here, be the circuit below for a simple inverter: simulate this circuit – Schematic created using CircuitLab When IN = 0, then the NMOS (M2) is (almost) an open-circuit and the PMOS (M1) is (almost) a ...


8

The purpose of the diode and MOSFET are for reverse polarity protection, not ESD. The diode is more simplistic, but it is lossy as it will drop some voltage across it (0.4 V to 1.0 V, depending on the type). The p-channel MOSFET should have a much lower voltage drop if chosen properly.


8

As above, what you have is a linear regulator. BUT If you add hysteresis to the circuit, you now have what is called a hysteretic converter, where the output bounces back and forth rapidly between slightly above and slightly below the desired output voltage. In this case, Q1 is now switching between off and fully enhanced (on) for much lower power ...


7

One problem with your design is if the overvoltage exceeds M2's maximum drain-source voltage, M2 won't actually disconnect the circuit. Another is that when it's tripped, you'll have significant current and significant voltage in D2 and R1 and they'll get hot, and maybe fail. The canonical solution for non-transient overvoltage protection is a crowbar ...


7

Did you see (and understand) Spehro Pefhany's comment? I take the liberty of turning it into an answer because that's also what I'd suggest. Add a diode in front of your circuit that shorts the voltage if the battery is reversed (=V2). In that case the (resettable) fuse will break the current flow. If the battery is not reversed (=V1) there is almost no ...


7

You have sortof the right idea: But the capacitor is in the wrong place. For slew rate control, it should be between the drain and the gate, not the source and the gate as you show it. Putting it between drain and gate causes feedback so that when the drain rises quickly, it turns the FET off more. Just a cap between drain and source can be good enough. ...


6

If cost is really such a high priority as you say, then why is reverse polarity protection needed at all? When it's more important that the circuit be cheap than robust, you make it cheap at the cost of robustness. If someone installs the batteries backwards, oh well, that's their problem. Of course the battery polarity needs to be clearly labled, but ...


6

The residual +1V that you are seeing is being caused by bias on the other signal pins to the uSD card. Current passes from either high levels on the microcontroller I/O pins connected at the SDIO interface or via the 47K resistors that you have on these lines into the controller chip in the uSD card. From there it passes through the input protection network ...


6

There are IC's which can provide this functionality. One option would be to use a "Power Multiplexor". An example is the TPS2115. It takes the place of the diodes and switches, and is controlled by a 2V-compatible logic signal. Its internal resistance is 110 milli-Ohm (or less), which give a voltage drop of 0.6 mV (!) at 5mA of current. You can find ...


6

The problem The /OE (output enable) pin of the 74CH595 toggles the output drivers between two states: driving the outputs (high or low) and high impedance (letting the output lines float). It is active low, so driving /OE low causes the 74CH595 to drive the outputs high or low depending on the data you have shifted in, while driving /OE high causes the ...


6

Yes, it's possible. But just like with a high-side NMOS switch, you'd need to drive the gate beyond the supply rail (below Gnd, in this case) in order to switch it fully on. While there's some motivation to use high-side NMOS switches — they perform better than the equivalent PMOS devices — there's no equivalent motivation to use a PMOS on the ...


6

To model the P-MOS transistor in LTspice you do not need to know the \$W\$ and \$L\$. The simples model used the \$K\$ factor and \$V_{TH}\$. The drain currency is equal to: $$I_D = \frac{K}{2}(V_{GS} - V_{TH})^2$$ And using the datascheetplot, we can also find \$V_{TH}\$ using this equation: $$V_{TH} = \frac {V_{GS1} \sqrt{I_{D2}} -V_{GS2} \sqrt{...


5

Consider the design to be sustainable, 2N7002 usually is used to control signals. You can use BSS84 as equivalent but pmos usually is used as power switch. that's why people rarely can find 2N7002's equivalent. They just use 2n7002 to turn on a PMOS power load switch.


5

The reason the FET turns off so slowly is because you only have 2 kΩ pulling it high. Take a look at the datasheet for that FET. It should show you the actual and effective gate capacitance when switching. The relatively weak 2 kΩ pullup is working against that capacitance. Here is a trick I sometimes use in this situation: The double ...


5

In The LTSpice help file you can find this table, which I'm too lazy to figure out how to reproduce completely: The table is under LTspice IV -> LTspice -> Circuit Elements -> M. MOSFET in the help file contents tab.


5

I think the top graph does indicate exactly where instability occurs: - The phase angle is zero degrees and the gain is still +45 dB. In other words it's "gain margin" that is causing oscillation here. The transient graph seems to indicate it oscillating at 250 kHz whereas the AC graph tells me it could oscillate at 100 kHz. This doesn't surprise me given ...


5

The MOSFET or diode are probably not being used for ESD protection. ESD protection usually uses a diode (TVS) in a configuration like this: Source: https://www.semtech.com/technology/esd-protection Both circuits provide reverse polarity protection. The diode has more loss (the smallest diodes have 0.2 V, and silicon diodes have 0.7 V. This means ...


5

The main reason is just to obtain a lower voltage drop and thus lower power loss in the device. An on-state FET can be modelled as a resistor, ideally a small one (a few mΩ is typical of power devices), while an on-state diode is more like a voltage source. For instance, say your device draws 100 mA from the supply. A diode with 0.7 V forward voltage at ...


4

T1 is a simple common emitter inverter. CNTRL_L0 is the input, and the node between T1 and Q2 is the output. If the input is high, the output is low. If the input is low, the output is high. Q2 is just another inverter, but it uses a MOSFET instead of a BJT, and because this is a P-channel device, everything is upside-down. In this circuit, as is ...


4

I designed for 12 volt NMOS technology some years ago. It uses saturated n-channel transistors for the pull-ups. As described by a previous contributor (List item #2 in this answer), this limits the output voltage to one Vt lower than VDD. The 5 volt supply is used for interfacing with TTL. The -5V supply is used to bias the substrate and bring the Vt to a ...


4

Microchip designer here... I've never heard of a "fat" MOS transistor, but there is such a thing as a "thick oxide" MOSFET transistor, sometimes referred to as just "thick" transistors. Typically, a MOSFET transistor is designed such that the electrical performance is good for a particular voltage range. For example, 0.7 to 1 volts. That means that it ...


4

As Ignacio is trying to say, you need to pull the gate of the FET up to the 350V supply rail to turn it off. This makes the VGS ~= 0V. Which means the FET is off. To turn it on, you need to reduce the voltage on this gate, perhaps the full 350V is not healthy for it. Perhaps drop the voltage at the gate to +330V to turn it on. This will make the VGS = -20V ...


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