# Tag Info

## New answers tagged pnp

3

Those are to provide a delayed start with sleep overriding the snooze.. Snooze and sleep are basically identical but sleep has a longer time constant and overrides sleep. It's all about charging C32 or C22 through different resistors. D2 is there to let sleep override snooze. Q8, C34, and R35 bypass sleep and snooze when power is first connected so there is ...

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The current path at Turn-ON. The capacitor is a short circuit. And the current path with the additional capacitor across $R_{57}$ resistor with a much larger capacitance value then $C_{CB0} + C_{LEAK}$ Now the BJT won't be able to Turn ON because $C_1 >> C_{CB0} + C_{LEAK}$ and we have a capacitive voltage divider thus \\$V_{BE} = V_{bat} \...

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From reading the question, and the operating condition of high dV/dT of collector_base voltage, you seek to understand the value of a capacitive voltage divider. Ok With rapid dV/dT across the Cap_ColBase (1.5pF, for example), the charging current needs to be absorbed somewhere, and NOT flow into the base_emitter region of the transistor. I'd plan to add a ...

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It's a ridiculously useless circuit of the kind that only university professors seem to think exist. Since 'beta' is 100, them Ib1=Ic1/beta. Same formula for transistor 2. From that you can calculate the 'biasing' resistors, taking Vbe ~ 0.6V. All 'operating points' can then be calculated. 'Real' transistors however have a wide range of beta, so it's truly a ...

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Q1: The high dV/dt causes a momentary current to flow through Ccbo+Cleak. This develops a voltage across R57 and turns on Q2. Where Iturnon = (Ccbo+Cleak).dV/dt Q2: Yes the added capacitor as suggested does indeed act as a voltage divider. It acts in the same way as a resistive divider where the result is R1/(R1+R2). For the capacitive divider the result is ...

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Here's an example schematic: Suppose top MOSFET is off, bottom MOSFET is on. Driver turns bottom MOSFET off, by outputting 0V to its gate. Then driver turns top MOSFET on. This creates high dv/dt as the SW node swings from GND to +12V. This injects current into the bottom FET gate via its Cgd Miller cap. If the bottom FET gate is connected to the driver via ...

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