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12

The part of the chip that does the management (the comparator, the voltage reference, the PWM generator and various low-level interface circuits) take some amount of current i.e. they are not self-powering and that's basically the main clue. They require current and that current/power quite often is provided by a low-level LINEAR regulator. Given that the ...

7

Besides of the self-consumption mentioned in other answers (that probably dominates loses in a well-designed circuit), there is one more V_IN dependence: switching capacitive loses. Output switch has internal capacity. It also probably has a snubber. Both of them charge at each switch either to 0 or to V_IN. These loses are proportional to V_IN squared and ...

4

Your solution (to the homogeneous as well as particular) is correct. If we solve the differential equations as usual, we need to plug in the initial conditions at $t=0$ while the initial conditions are given at $t=\alpha/\omega_0$ in the book. That is why you seemed to have ended up with an unknown $(I_0 - I_2)$ in your coefficients and missing a $(-\... 4 The regulator itself consumes current. It has an internal linear LDO to drop input voltage to useful levels. And therefore, LDO losses are higher at higher input voltage, even if the circuitry powered by the LDO uses exactly same amount of power. 4 Gate Driver will not produce 0.2 nanosecond edges. The required charge must flow from 2nanoHanry to 10nanoHenry inductances in the gate driver's GND, VDD, Vin (03/3v?) and Vout (0/12v?). Given 2nH and 2nF are SLOW edges ( 60MHz ringing), you should alter your edge rate expectations. 3 As the others explained, the regulator draws some current from the input in order to function. This will be current to power internal circuitry plus a variable current to charge the FET gates that is roughly proportional to switching frequency. Let's call this total quiescent current Io. Since the internal LDO wastes excess voltage as heat, it'll use a power ... 3 a) Advantage is if you need 3.3V too and the 1.8V cannot handle 12V input. Also any 1.8V converter can be used as it does not need to handle 12V input. Disadvantage is more power losses and heat production in each conversion, and the 3.3V converted needs to be larger to support also the power for 1.8V converter. b) Advantage is usually that there are less ... 2 1.) whith positive voltage current will flow through Q2A and as it is a current mirror, it will also open Q2B. Together with the parasitic diode of the mosfet, it will rise the voltage at R24. This will open the mosfet -> normal operation. In case of under/reverse voltage, the circuit will close the mosfet (current mirror has a high gain, so it will ... 2 this causes some relays to stay energised for a second or two after power supply is cut off which is not ideal. ... what can cause a relay to stay energised after supply is out? Relay coils have pick up and release voltage ratings. Most relays can pick up at 75% of rated coil voltage and can remain until the coil voltage drops down to even 30%. The ... 2 Your implementation seems to be correct and working properly. It is difficult to see from your waveforms alone if you're having a mistake in your SVM implementation, since you're not showing it. There are several ways to implement SVM (either using the conventional way of calculating the Dwell times that form the space vector or using a conventional Sine-PWM ... 2 I am suspicious of V2,V3 and V7,V8 possibly being the wrong way around... Generally one should spice small bits of doings, running a whole system seldom ends well because it just gets madly slow even if it converges at all. I would loose most of the +-15V power stuff, one of each will be quite sufficient and will make the model much simpler. I would also ... 2 C_GD2 is called the "bootstrap" capacitor. When the MOSFET is off it charges up to VCC<->Source voltage trough bootstrap diode D_GD1. When the MOSFET has to turn on the chip will connect VB to HO, effectively putting the charged capacitor in parallel with the MOSFET gate-source. As the MOSFET turns on the source begins to rise towards V_BAT(x)... 2 AJN nicely answered (+1) - I'm just putting the following as an answer so i can show detail and pictures. I find that using Laplace to solve circuit problems algebraically is often times easier than wading through differential equations. I'm much better at algebra than d.e. For example, below i will solve this case for the inductor current: Transform to ... 2 Most likely heat damage and/or hot connect surge currents in power supply, get adequate voltage from datasheets for case size and cap value for 19.5V chargers. Then Learn that Laptop chargers hot inserted burn out connector contacts and caps, same with USB 12W on lightning connectors, even tho no OEM ever tells anyone in public about this.!!!!! Gold plating (... 1 In diagram 'b' I would expect M3 and M4 to have higher gain from Vin to Vout and less Miller feedback as they are separated from the output by M1 and M2. This lower feedback will also result in less capacitance loading on the previous stage giving a faster transition time. Possibly less energy consumption per transition (lower power consumption when cycling).... 1 An op-amps internal power dissipation is due to its output being a class AB stage (usually) and they are about 60% power efficient in delivering load power. In other words, if the load power is 60 mW then the op-amp will be dissipating 40 mW. But this is at maximum peak-to-peak output voltage. If if the op-amp is required to deliver only half the maximum ... 1 In a thermistor the resistance will change due to heat which is generated by the amount of current flowing through it. The resistance at 25 degrees C will be 10 ohm and then decrease as more current is flowing through it and it heats up. So the answer is no, it will not be unchanged up until 1.5A. It would be at a higher resistance if the line on the graph ... 1 Question: "How come do we call the stated oscillator a nonlinear circuit?" Each oscillator is and must be - per definition - a non-linear circuit. This is because for a safe start of oscillation the closed-loop pole pair must be in the right half of the s-plane (loop gain >1). As a consequence, the oscillation amplitudes continuously are growing ... 1 i = C*(dv/dt), ignoring ESR and inductance. If your rectified voltage is sinusoidal in shape when the diode is conducting you can differentiate the sine wave and calculate the maximum current. 1 Q point is the point where a non-linear circuit (like diodes, transistors, etc.) can be approximated by a linear circuit, and we get a DC set of voltage and current of that non-linear circuit. 1 You are not looking at the lamp voltage, but at two points relative to ground (VF1, VF2). What you see is right. If you really look at the voltage of the lamp, it will look the way you expected it to: 1 The outcomes of the Clarke transform are correct. The alpha component corresponds directly to the$u_a$voltage and the beta component corresponds to the line-to-line voltage$u_{bc}$scaled by the factor$\frac{1}{\sqrt{3}}\\$. This is also answer to the second part of the question because the line-to-line voltage of the voltage source inverter has ...

1

With a brushed DC motor, it's relatively easy. One way to express it is that you measure the resistance of the motor, and calculate the stall current. However, as the resistance of brushes varies somewhat with current, you need the resistance at the stall current, so to get that accurately, you end up measuring the stall current anyway. But however you do it,...

1

The proper way to do this is: Use a grid-tie inverter. This is one that synchronises the AC from the inverter with the AC on the mains. The grid tie inverter will have safety features to ensure that if mains fails that the inverter will not put power out on the grid and possibly electrocute a lineman. Now you have two feeds into your house. The loads will ...

1

Since you're using the VCSW, it looks like you're after a simple, behavioural model, not a real-life case. Therefore U1, U2, and U3 (+ sources) can be replaced by two voltage sources of fixed pulse-width (say 1 Vpk), and you could try to help the simulation by using a better behaved .model for the VCSW: .model sw sw ron=10m roff=10meg vt=0.5 vh=-0.5. If you'...

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