# Tag Info

15

There is no free lunch here. You need a solid test plan. This is an area well worth investing in, because once you develop a reputation for shipping shoddy products, it's pretty much impossible to shake it. To a large extent, you need to be able to trust your component suppliers, and focus on testing only for the types of errors that occur during the ...

14

It certainly depends on the type of module. For example, I don't think any product developer would use a DC-DC converter module, they're way too big, too expensive, and a EE can design their own using a tiny (3x3 mm) IC and a few extra components in an afternoon. However when you get into wireless modules, that is a different story. For example, I have ...

13

Electromagnetic Interference is a radiated or conducted signal that is unwanted that you are trying to avoid. Electromagnetic Compatibility encompasses the standards and testing of equipment so that it can generally be expected to function properly in a shared environment. This involves testing devices to make sure that the EMI produced is under some limit, ...

11

Note: Question can be interpreted as a design problem, I'm addressing it as such. If you want to test the FTDI chip I would leave out the FPGA. If you use that you'll be testing two things at once, and not know where the error is in case it shouldn't work. The loopback is a good idea, but I would go directly from FTDI output to its input, and connect ...

11

The pins used for making the kind of test fixtures, which the O.P. is describing, are called: contact probes, or spring loaded pins, or pogo pins. They come in various sizes and with various shapes of tips. The choice of a tip depends on the type of test pad: via, flat pad, pin from a throughole component on the solder side. Here's a datasheet of the pogo ...

11

Designers already use modules: they're called integrated circuits. If you look at the aliexpress modules, they nearly always comprise an IC surrounded by a few discrete components on a small PCB with headers. If you're building a cost-optimised product, you can very easily save size, weight, and cost by just putting the IC and its support components on your ...

10

The test board arrangement referred to is commonly known as a Bed-of-Nails board. The pins used are called pogo pins or spring-loaded test probes: (source: eBay) Pogo pins come in a variety of contact shapes: Yes, specific test points, and pogo pins in corresponding locations, would be good - else the pogo pins would simply press against random parts of ...

10

That is, no contact. I've currently come across 2 cold soldering and 3 no contact issues. Looks to me you have got a hole in your final testing. (I assume you have some sort of test-jig) I can imagine that waiting for a GPS lock requires too much test time but, especially with the detected errors you should add a resistance/contact/SWR test on the antenna.

10

In theory, you shouldn't need it on a test pad. In practice, you may need it on a test pad. In reality, I've never fitted it to a test pad. ESD protection should be applied to everything which would be exposed to a non-ESD protected environment. This means that every single bit of exposed metal that is touchable by anything outside of an ESD controlled ...

10

That depends on the purpose. If your module is a kind of sample / prototyping platform and you will access the test points often, consider adding ESD protection. If this is a final product and the pads will be used once in a lifetime during the production test (supposedly in a controlled ESD-free environment), ESD protection will just increase the cost for ...

10

There are a number of reasons for cracked vias and virtually all of them are caused, to a greater or lesser degree, by CTE issues. Looking at this datasheet (a very commonly used material in the high reliability sector) we can see that below Tg the CTE in the Z axis is typically 45 ppm / K (*) but in the X and Y axes it is typically 13 to 14 ppm / K. ...

9

There are various methods of modelling yield that are appropriate during different process steps. The most conservative is the exponential rule and therefore the safest to model with (you will produce more die per wafer than predicted). $Y = Ke^{DA}$ Where D = Defect density, A = Area, K is a scale factor and Y = Yield. This equation allows you to ...

9

Yield rates are definitely a commercial secret; they will likely vary from batch to batch with normal manufacturing variation and attempts to tune the process to increase yield. Yield is inversely proportional to die size. The i7 die size for "Lynnfield" is 296 mm², according to wikipedia, which is pretty big. Yield is also traditionally low on newer ...

9

There are few methods to accelerate GPS module assembly testing: Use AGPS to acquire a faster fix. TTFF should take few seconds, assuming you can load the AGPS data to the unit. Read the GPS raw data, specifically, C/n. Use a GPS repeater, or better yet, a GPS constellation simulator to get a known signal.

8

Yes, this sort of thing comes up regularly. We have settled on a system that works pretty well for small boards. Here is one example: The top part is hinged at back and swings up. You then place the board to test in the cradle for that purpose: What you can't see in that picture are the pogo pins that stick up from the tester under the board. When the ...

8

Putting in those pads first time round is called DFM (Design For Manufacture). And it sounds like they're giving you a good price on the bed of nails. Either get this flow working (it's perfectly normal) or ask your next fab house if they have a flying probe tester in house. One way to economise is to use bed of nails ONLY for nets that don't already ...

7

I add test points to a majority of the boards I work on - unless the client specifies otherwise. I won't add test point for every net, but power and ground nets definitely get a test point. When we get a batch of boards back from the fab house, I grab the DMM and "Ohm out" the test points, to make sure nothing is shorted to ground. We mostly do very low ...

7

Another consideration in addition to davidrojas' and the other answers, is that if I as a manufacturer decide to use another commercial product (note: this isn't outsourcing to another company to make my product, but actually purchasing a commercial 'module' as you specify), then I am forever on having to live with it. There are two serious problems there: ...

7

Headers are pretty cheap and make a lot of sense over a wide range of quantities, down to 1 piece. A 5 x 2 header takes up very little space, even less in 2mm pitch. The connections usually end up free of flux so they don't crud up the mating connector. For really high volume, you can use a fixture with spring-loaded 'pogo' pins which can be cheaper per ...

6

For very small boards, you can test before depanelizing. Bring the test points out into the panel, through an inner layer so the depanelization process doesn't tear up the rest of the traces. Or just use smaller probes. Semiconductors are tested before sawing up the wafer, using machines that are maybe 60 dB more expensive than pogo pins in a circuit ...

5

There is no one single number which represents yield of a manufacturer. The yields vary between technologies, fabs and dies. It also varies with time. In general, when the technology is just released and is not mature, the yields will be low. Process engineers work very hard in order to enhance the manufacturing process and obtain high yields. The reasons ...

5

I am working for such a company but am mainly situated in the development, so I have some insight but there are probably people out there who know much more: When it comes to testing, we follow various approaches. Basically we start with AOI (Automated Optical Inspection). This is rather cheap and reveals many errors before any further steps are done which ...

5

Pogo pins are designed to be placed in pogo pin receptacles or sockets, slightly larger sleeves made of similar material. Your P50 pogos would use an R50 socket, P75's would use an R75 and so on. Knowing that will drastically improve your chances of finding an online vendor. Common socket forms have an indented rear to which fine wire can be soldered and ...

4

Always have the bare board (PCB) 100% tested against the netlist you supply. If you are depending on controlled impedances, have the board fab for that too. JTAG doesn't add to the cost of the board or require additional chips, just a connector. But make sure you can seperate the chains, e.g. one for a FPGA and one for a processor. Flying probes avoids the ...

4

As gbulmer says, panelize.ulp is an Eagle tool that does this. There are some clear drawbacks to using this tool, IMO- mostly with respect to how all the components end up numbered. There are some usable tools, like gerbmerge (see http://www.instructables.com/id/Panelizing-PCBs-for-Seeed-Using-Eagle-Free-Light/) that do a very reasonable job, for free. ...

4

If you are designing for a European market start with the directives that are needed to CE mark your product. These are all freely available on several websites. Work down these to decide what directives are applicable then it should become clearer what EN documents are required to be adhered to for your product. Here is a good starting point. It's the UK ...

4

Normally the hole size you specify in your EDA program will be the finished hole size within some tolerance. However, there are a (very) few manufacturers who interpret this as the tool size, so the hole may be somewhat different in size (-0.1mm in the case of one supplier) so it's best to check with your manufacturer. For round holes you definitely don'...

4

You're not really testing the complete board if you don't stick an RJ-45 in the socket because there is significant circuitry inside the magnetic jack. For example: As @JRE says, it may not work with two transformers in parallel, or it might. One approach would be to simply use a duplicate jack (as used on the PCB) in parallel and plug your test computer ...

4

Short answer: Yes - a bed of nails is a good way to accomplish test of your product. Disclaimer: I work as a test design engineer creating testers for this purpose. Here is what I can add: Create a detailed test specification. Whether you or someone else creates a system to test your product, you’ll need clear documentation on what and how accurately ...

4

A faulty antenna connector will result in a degraded signal strength. This can vary anywhere from total loss to almost full signal strength. Optimally you'd have a GPS simulator with known transmission strength, and check the received signal strength on each module. In my experience you can get GPS timestamp with much less signal strength than is needed ...

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