14 votes
Accepted

What would make me choose Verilog or VHDL over schematic design on CPLDs or FPGAs?

Schematic design is only useful when you're only tying together a few off-the-shelf modules (counters, adders, memory, etc). But implementing an actual algorithm (say, a cryptography hashing algorithm)...
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  • 2,789
14 votes

Discrete logic design

I'm not a professional electronics engineer at all (actually just a beginner), but my few cents are that dedicated discrete logic ICs should only be used if timing is important or if it is a ...
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14 votes
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Discrete logic design

Discrete logic design won't be fully phased out. There will always be applications where using a discrete logic IC is preferable. As has been pointed out, speed is a big advantage, although in a lot ...
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  • 11.5k
12 votes
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Counter for 20 GHz clock

15 years ago I designed a two parameter digitizer (energy and time) to measure time of flight. For this system I used a constant current source into a cap held in reset by a JFET. On receiving the ...
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12 votes
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Is it possible to replicate the ENIAC using logic gates

The ENIAC used logic gates, they were just made up of vacuum tubes. The ENIAC had thousands of them. 6,550 out of the 18,800 tubes in the computer (circa 1946) were dual-triode 6SN7GTs. Each tube was ...
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  • 47k
10 votes

What's the difference between CPLD and an FPGA?

Differences: Capacity - CPLD usually has less capacity of logic. The largest CPLD may be at a similar level of the smallest FPGA in the mainstream market. Storage of the image - CPLD can boot by ...
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  • 219
10 votes

Discrete logic design

If you're going to create a commercial product, you really shouldn't choose a design because "it's programmable" or because a more senior colleague proposed it. Instead you should estimate risks and ...
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9 votes
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Can a CPLD be reprogrammed just like a Microcontroller?

No, and it probably illustrates the risk of looking at something that's been transcribed from a list or whatever rather than the original source. The original datasheet you linked (primary source of ...
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9 votes
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Please explain this price difference

Yes, of course, supply and demand. But let me make a few comments on manufacturer costs. Newer IC's are typically built on newer fabs which can fit more transistors in a smaller area. Because of this, ...
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9 votes

CPLD is (sometimes) not incrementing counter

Is the trigger input completely asynchronous to the 50MHz clock? If so, it probably violates the setup and hold time requirements from time to time. You need to ...
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  • 165k
8 votes

Can I use C language to program a CPLD/FPGA?

Generally you can. There is free SystemC for HLS(High Level Synthesis). HLS is getting more and more popular but what you have to remember is that you do not program CPLDs /FPGAs using C language, you ...
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  • 697
7 votes

MITM on I2C Bus

I think that attempting cutsey hacks like you have been is asking for trouble, with exactly the kind of symptoms you are running into. You are basically trying to cheat and hope you don't get caught. ...
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7 votes
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CPLD is (sometimes) not incrementing counter

Fist of all:Your trigger is coming in a-synchronous to the clock. You must first synchronize it before you can safely use it. The code for that is: ...
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7 votes

Discrete logic design

One aspect the other answers are forgetting is safety. Discrete logic circuits are way more reliable than much more complex microcontroller designs. I helped building a hydrogen prototype car, all the ...
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7 votes

CPLD based Pierce oscillator

This CPLD has Schmitt trigger inputs so I guess this should be possible. Actually, if it has Schmitt trigger inputs it makes it impossible. A Schmitt trigger would just about guarantee that the ...
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6 votes
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what to do with JTAG pins when idle?

I would suggest referencing the specksheet for the specific device - they usually have pretty extensive documentation and try to cover most of questions. Here's what I found in my family of devices: ...
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  • 3,074
6 votes

Counter for 20 GHz clock

Some long while ago, as a thought experiment, I 'designed' a time capture FPGA. It had a ring oscillator, conventional other than the fact it had 41 inverters. The period was thus much much lower ...
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  • 142k
6 votes

Counter for 20 GHz clock

As someone already pointed out, there are dedicated ICs for that purpose. If you want to do it on your own a possible approach would be to use so called Vernier delay lines. You have two delay lines ...
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  • 7,975
6 votes
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PAL data with ADC?

It is not practical to resolve an NTSC or PAL type analogue video data into a digital format using a typical microcontroller A/D converter. The equivalent pixel density of the analogue signal is 13.5 ...
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6 votes
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Can an EPROM be "refreshed" without UV erasing?

When the EPROM is erased, all the bits are typically read as ‘1’, so each byte is 0xFF. That is the way they will tend to age, with time and high temperature or radiation. If you don’t have access ...
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6 votes
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How do you cast an integer as a time in VHDL?

multiply (or operate otherwise) by the time unit constant t_per : time := (1 / input_frequency * 1000000000) * 1ns; (or variations thereof)
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  • 935
6 votes
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CPLD based Pierce oscillator

I do not recommend this approach. You may get some circuit to oscillate under some conditions but you may very well have problems with jitter, unreliable startup and off frequency operation. You ...
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5 votes
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Create delay shorter than a clock period in CPLD

No, asyncrhonous delays are not synthesizable constructs in an HDL. However, if you don't require a lot of accuracy, you can artificially specify a long string of gates (e.g., inverters or buffers) ...
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  • 165k
5 votes
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4 port 12 bit mux is consuming 48 macrocells!

Instead of implementing the mux as a gate-level logic, which may confuse the synthesizer, try to use some behavioral or RTL description, that will allow the synthesizer to choose the way to implement ...
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  • 9,612
5 votes
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What's the difference between CPLD and an FPGA?

CPLDs are generally only used for replacing a relatively small amount of discrete logic. Namely, things like a bunch of address decoders and bus interface circuitry. CPLDs contain very little memory;...
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5 votes

Counter for 20 GHz clock

FPGA fabric, as other answers point out, cannot be clocked at the rate you need. However, some FPGAs also have high speed serial interfaces in the 5Gb/s to 10Gb/s range, intended for SATA, PCIe and ...
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5 votes

Dividing numbers on an FPGA

Our Open-Source PoC-Library has a multi-cycle division IP core, which can be synthesized as a pipeline. The bit count of the dividend and divisor as well as the radix can be configured to the users ...
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  • 3,807
5 votes

74LS161 in program counter circuit jumps clock cycles

As far as I can see, you don't have any power supply decoupling capacitors anywhere on your collection of breadboards. It's no wonder it's "touchy" and sensitive to glitches. You should put about 100 ...
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  • 165k
4 votes

What would make me choose Verilog or VHDL over schematic design on CPLDs or FPGAs?

A couple of practical aspects in addition to Jay's excellent answer: Bugs. The schematic tools tend to be buggier* than the rest of the toolset. This is possibly due to the preference of Verilog/VHDL ...
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4 votes

Can a microprocessor ( specifically the ALU) be considered as an FPGA that is re-programmed by the Instruction Decoder

No, an ALU is not in any sense an FPGA. All of the functions of an ALU are hard-wired (predetermined), and the desired result is selected by the instruction decoder. In contrast, the logic elements ...
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