23

I've used a product line called the Electronically Programmable Analog Circuit (EPAC), probably more than ten years ago by now, which claimed to be the analog equivalent of an FPGA, and Cypress has for years produced a line called the PSoC (Programmable System On Chip) which incorporates a switchable arrays of both analog and digital circuitry. Note that in ...


15

Discrete logic design won't be fully phased out. There will always be applications where using a discrete logic IC is preferable. As has been pointed out, speed is a big advantage, although in a lot of applications, the speed difference is just not that important. When it comes to the design phase, if you design a circuit that only needs to perform 2 or 3 ...


14

Hard connection of a pin to the VCC or GND is o.k. from a functional standpoint for high impedance inputs such as CMOS logic inputs. It also happens to be convenient on PC board design where it eliminates an additional component. There are several conditions under which having an input pulled up or down via a resistor would be better than a direct rail tie. ...


14

Schematic design is only useful when you're only tying together a few off-the-shelf modules (counters, adders, memory, etc). But implementing an actual algorithm (say, a cryptography hashing algorithm) is nearly impossible to do without an HDL (like VHDL or Verilog), since there's no way to describe a system at a behavioral level with schematic symbols. ...


14

I'm not a professional electronics engineer at all (actually just a beginner), but my few cents are that dedicated discrete logic ICs should only be used if timing is important or if it is a requirement not to use programmable logic. With a microcontroller you can implement much more complicated logic and it is more flexible. Also it can be reprogrammed ...


12

15 years ago I designed a two parameter digitizer (energy and time) to measure time of flight. For this system I used a constant current source into a cap held in reset by a JFET. On receiving the trigger (NIM fast logic, level shifting kept in the analog (as opposed to saturated switching) regime, the JFET opened, and I was able to achieve 50ps resolution ...


10

Differences: Capacity - CPLD usually has less capacity of logic. The largest CPLD may be at a similar level of the smallest FPGA in the mainstream market. Storage of the image - CPLD can boot by itself while most of the FPGA need to fetch the configuration bitstream from non-volatile storage because they are SRAM based. This impacts the security of the ...


10

The ENIAC used logic gates, they were just made up of vacuum tubes. The ENIAC had thousands of them. 6,550 out of the 18,800 tubes in the computer (circa 1946) were dual-triode 6SN7GTs. Each tube was used as a flip-flop and represented one bit, one side the 1, and the other side the 0. The ENIAC used ten-position ring counters to store digits in ten's ...


10

If you're going to create a commercial product, you really shouldn't choose a design because "it's programmable" or because a more senior colleague proposed it. Instead you should estimate risks and costs associated with each design, and pick the one with the lowest cost and acceptable risk level. For a start: price of individual components adds to the cost ...


9

No, and it probably illustrates the risk of looking at something that's been transcribed from a list or whatever rather than the original source. The original datasheet you linked (primary source of information) lists the endurance at 1,000 erase/write cycles minimum (page 14).


9

Yes, of course, supply and demand. But let me make a few comments on manufacturer costs. Newer IC's are typically built on newer fabs which can fit more transistors in a smaller area. Because of this, they can get many more IC's from a given amount of silicon. So the manufacturer cost is higher on older IC's. This is very significant. In competitive markets, ...


9

Is the trigger input completely asynchronous to the 50MHz clock? If so, it probably violates the setup and hold time requirements from time to time. You need to synchronize it to the clock through at least two FFs before you use it in any decision making. I can hear you saying, "But it's only used in one if statement. If the trigger_state gets updated, ...


8

You could add an extra UART over SPI or I2C. These have internal FIFO buffers inside them so you periodically check them for content and let them handle some buffering. NXP, TI, Maxim probably offer these parts. MAX3100, SC16IS752 etc. You could also add a second MCU to do this, but as you're already using quite a simple microcontroller with 1 UART and want ...


8

Generally you can. There is free SystemC for HLS(High Level Synthesis). HLS is getting more and more popular but what you have to remember is that you do not program CPLDs /FPGAs using C language, you rather describe hardware using C language. To make it work on real hardware you need vendor specific HLS tools. In my opinion, writing synthesizable ...


7

This is an interesting question. From personal experience, I have left FPGAs powered up for hours in an unprogrammed state while performing checks on the rest of the circuitry when a new board comes in from the assembly house. I have not noticed any detrimental effects from doing so. But I've honestly never thought about it. I looked around to try and find ...


7

You'll have to begin with detecting the start condition: SDA going from high to low while SCL is high. This should reset your I2C logic. Then shift in 8 bits (count them) and after the eighth bit is received compare the address with the CPLD's address (the first 7 bits). If they match pull SDA low until the next clock pulse. Don't forget that this should ...


7

The code you show is essentially a priority encoder. That is, it has an input of many signals, and its output indicates which of those signals is set, giving priority to the left-most set signal if more than one is set. However, I see conflicting definitions of the standard behavior for this circuit in the two places I checked. According to Wikipedia, the ...


7

I would step up to a cheap ARM. You can get the Freedom Board which is a Cortex-M0+ which can run up to 48Mhz. Also being an arm you will get 32 bit registers so you can do more per op-code. Also it has a DMA engine so you might be able to off load the loading of the LEDs to DMA while the processor updates the memory. You can get them from Digikey as well ...


7

One aspect the other answers are forgetting is safety. Discrete logic circuits are way more reliable than much more complex microcontroller designs. I helped building a hydrogen prototype car, all the safety-circuits were designed using discrete logic. Safety and reliability is an aspect you'd might want to consider designing an alarmsystem.


7

This CPLD has Schmitt trigger inputs so I guess this should be possible. Actually, if it has Schmitt trigger inputs it makes it impossible. A Schmitt trigger would just about guarantee that the oscillator would start up in a mode that excites the RC components of the circuits and bypasses the crystal altogether.


6

I would personally use tri-state outputs in this situation. Instead of driving a 0 or a 1, you could have pull-down (or pull up depending on your preference) resistors on the outputs, and drive the pin you're interested in high or low - the opposite of your chosen pull-up/-down resistor. The other outputs should be set to high impedance so they don't ...


6

I would go for the buffer. You would never have to worry about not delivering enough current or any damage to your CPLD. Now you can use 300 transistors if your really want to but I would suggest using Darlington transistor arrays. They come in many different flavours, most giving you 7 inputs and outputs at a few hundred mA per channel. See here: http://...


6

I am referencing the Spartan 3 datasheet, since that's the FPGA I'm most familiar with. If you look at chapter 2 (Functional Description), the section "Configuration" has a couple flow diagrams. Figure 27 (page 50) shows the flow diagram for loading from Flash. Figure 28 shows the JTAG flow diagram. Here's a brief summary. 1) Wait for Vccint, Vccaux, ...


6

The best way (depending on how complex your final design will be) would probably be to use a separate fast CMOS oscillator for your CPLD system clock, and have it process the input pulses and output the stepper pulse. This way, the clock is running all the time when the system is on, and it can time the period from the last input pulse - if it's above a ...


6

ThePhoton's answer is an excellent one. I would like to add some additional information here for your consideration. This stems from the fact that even though we have state of the art fancy FPGA and CPLD devices using HDLs and systhesis tools it can be informative to look closely at things designed years ago. Stay with me while I walk through this to my ...


6

(a) My own preference is (strongly) for VHDL - in many ways, with VHDL, you know where you are, more accurately, than in Verilog. I described some of these ways in this answer and another answer there gave this useful link. VHDL is said to be more verbose, but I find that its HLL features let me create hardware at a higher level, and that offsets the ...


6

I would suggest referencing the specksheet for the specific device - they usually have pretty extensive documentation and try to cover most of questions. Here's what I found in my family of devices: XC9500, XC9500XL, XC9500XV, and CoolRunner XPLA3 have internal pull-ups on TDI and TMS. CoolRunner-II devices have internal pull-ups on TDI, TMS, and TCK. It ...


6

Some long while ago, as a thought experiment, I 'designed' a time capture FPGA. It had a ring oscillator, conventional other than the fact it had 41 inverters. The period was thus much much lower than the delay of any gate. The FPGA process had individual gate delays down in the 10s of pS where the routing was local and the fan-out low, but could only ...


6

I think that attempting cutsey hacks like you have been is asking for trouble, with exactly the kind of symptoms you are running into. You are basically trying to cheat and hope you don't get caught. The one thing you haven't tried, according to your description, is a full emulation of this card reader thing. You haven't really explained what exactly it ...


6

Fist of all:Your trigger is coming in a-synchronous to the clock. You must first synchronize it before you can safely use it. The code for that is: reg sync_trigger,safe_trigger; always @(posedge clk) begin sync_trigger <= trigger; safe_trigger <= sync_trigger; end The behavior your are seeing is because the hardware will more look like this: ...


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