37
votes
Why do FPGA projects always take the same amount of time to compile?
With software ... if we change a single file in the project, everything does not need to be compiled again.
Only if your compilation creates intermediate files to avoid recompiling unchanged files.
...
- 57k
25
votes
Accepted
Can FPGA out perform a multi-core PC?
A colleague of mine benchmarked this and came to the conclusion that FPGAs would outperform a PC once you had more than about 100 independent, integer tasks that would fit in the FPGA. For floating ...
- 45k
21
votes
Accepted
FPGA starts working after irrelevant changes, why?
Your uart_rx signal is asynchronous to your clock. However, you have one place in your code where you use it directly in the state machine. This is curious, because ...
- 165k
20
votes
Why do FPGA projects always take the same amount of time to compile?
This is because of how the FPGA toolchain works. There are several main steps: synthesis, mapping, placement, and routing. Synthesis is the only one that is similar to compilation. Synthesis is ...
- 39.7k
19
votes
Can FPGA out perform a multi-core PC?
An FPGA works completely differently from a processor.
For a processor you write software that tells the hardware what to do.
On an FPGA you describe "what the hardware should look like" internally....
- 2,165
18
votes
Is using floor plan tool during FPGA design ever actually useful or required?
Since nobody has answered, here are a few things you can do in the floorplanner (my experience is with Xilinx tools, but I expect the others are similar):
Verify "visually" that some ...
- 121k
16
votes
Why do FPGA projects always take the same amount of time to compile?
Because in software, there is a linking phase. The linker takes all objects files (resulting from the compilation of each source files), and only alter the function calls so that everything works ...
- 15.5k
14
votes
Quartus Can't fit design into Device, is there any way to optimize it to get it to fit?
I'm afraid you're making a classic Verilog/VHDL mistake: trying to write a computer program in an HDL, instead of using it to design a digital logic circuit.
An FPGA has no CPU to run Verilog 'lines' ...
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13
votes
Can FPGA out perform a multi-core PC?
It depends a lot on the algorithm, but the principle can be explained quite simply.
Suppose that your algorithm has to sum a lot of 8-bit numbers. Your CPU will still need to fetch each instruction, ...
- 13.2k
10
votes
Accepted
Altera FPGA I/O weak pull ups
There are two ways of doing it.
1. Pin Planner
The first approach is in the Pin Planner tool. This is the GUI that allows you to select which pin goes where. From the main window with your project ...
- 57k
10
votes
Accepted
Is using floor plan tool during FPGA design ever actually useful or required?
Why would one ever need to use these floor plan tools to lock design logic into specific regions? Is there any benefit to doing this? Is this ever really required?
There are certainly reasons why it ...
- 57k
9
votes
Accepted
Altera Quartus "Warning (18236): Number of processors has not been specified...", how to suppress?
Add this tcl expression...
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
... to either assignment_defaults.qdf or the .qsf file. Both should be in the ...
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9
votes
Accepted
UART receiving random values
The problem is sending constant data stream without any pauses between symbols.
The ASCII symbol 'S' has a value of 0x53, so it is sent over the wire as repeating pattern of 0110010101 which includes ...
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8
votes
Why do FPGA projects always take the same amount of time to compile?
NOTE (not explicit in other answers): FPGA build tools and software build tools both have to fit the end-product into a space. For software it's a logical address space, and the spatial relationship ...
- 2,295
8
votes
Is using floor plan tool during FPGA design ever actually useful or required?
The other answers already give several important points and I'll add another:
When you work in a safety critical environment, you might want to spatially separate functions in order to harden them ...
- 103
7
votes
Accepted
How do I generate a schematic block diagram from Verilog with Quartus Prime?
Use the "Netlist Viewers" in the "Tools"-menu. The RTL-Viewer creates a hierarchical expandable diagram. Layout can be horrible at times.
- 1,730
7
votes
Is using floor plan tool during FPGA design ever actually useful or required?
Yes, it is very useful for a number of things, mainly to get insight into what the tools did with your design. It's especially useful when working on timing closure.
From the floorplan, you can ...
- 39.7k
6
votes
Can FPGA out perform a multi-core PC?
There are roughly 3 levels of specialization of computing equipment:
CPU (like in your laptop) is the most generic of them all. It can do everything, but this versatility comes at a price of slow ...
- 1,695
6
votes
Accepted
Bus to wire in quartus
Just connect it up directly with a wire (you will see a little blob appear to show it is connected). Then, name the bus something like name[msb..lsb], and then name ...
- 57k
6
votes
How do I generate a schematic block diagram from Verilog with Quartus Prime?
Seeing that you're using a Lite version of Quartus, maybe you don't actually are interested in Altera synthesis, but more in general Verilog analysis and clever code optimization.
You might want to ...
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6
votes
Why do FPGA projects always take the same amount of time to compile?
I have used incremental FPGA compile in the distant past without any design partition, but IIRC it failed every 1 in 2 or 3 attempts and I ended up doing a full compile anyway.
However, if you have a ...
- 91
6
votes
Help me debug these VHDL errors please
This is not specific to VHDL, but generally here's how to interpret compiler error messages:
Error (10500): VHDL syntax error at clothes_washer.vhd(22) near text ")"; expecting an ...
- 13.4k
6
votes
Quartus Can't fit design into Device, is there any way to optimize it to get it to fit?
A running average can be implemented with just the buffer, one register, an adder and a subtractor. It doesn't need to take many resources.
Image credit - https://surf-vhdl.com/how-to-implement-...
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5
votes
Can FPGA out perform a multi-core PC?
Yes, FPGA can outperform modern CPU (like Intel i7) in some specyfic task, but there are easier and cheaper methods to improve neural network performance.
By cheaper - I mean total effort, not FPGA ...
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5
votes
Accepted
Benefits of using Altera IP in FPGA designs?
For primitives, absolutely no benefit performance wise. The only use is it means you don't need to create files with your own primitives in, but if you rely on the Altera ones then migrating to ...
- 57k
5
votes
Altera FPGA I/O weak pull ups
I would like to point out that the weak pullup resistors on an FPGA/SOC/MCU are not a replacement for real external pullups. So when devising a strategy to use it please take the following into ...
- 55.3k
5
votes
FPGA maximum frequency : limiting factor
I suspect the difference is due to the negative coefficient in the 2nd case (according to the order of your diagrams).
Because your multiplying coefficients are all powers of 2, your multiplies can ...
- 121k
5
votes
UART receiving random values
As an addition to Justmes answer (feel free to combine this into your answer):
This is a UART Transmission of an S:
This is what happens if you dont have an idle:
And this part is what the receiver ...
- 4,731
4
votes
Altera FPGA I/O weak pull ups
Within the qsf file, you can add the following:
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to pin_name
4
votes
Using a mif file in Quartus
You can use the memory IP cores to create a memory with initial mif content. You can check the IP core user guide for more information.
Another solution is to use VHDL attributes to initialize the ...
- 1,159
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