24
A colleague of mine benchmarked this and came to the conclusion that FPGAs would outperform a PC once you had more than about 100 independent, integer tasks that would fit in the FPGA. For floating point tasks GPGPU beat FPGA throughout. For narrow multithreading or SIMD operation then CPUs are extremely optimised and run at a higher clock speed than FPGAs ...
21
Your uart_rx signal is asynchronous to your clock. However, you have one place in your code where you use it directly in the state machine. This is curious, because in all other cases, you are careful to assign it to rx1 and then test that.
IDLERX: begin
rx_bitcount <= 4'd0;
rx_busy <= 1'b0;
if (uart_rx == 1'b0 && rx_err !...
19
An FPGA works completely differently from a processor.
For a processor you write software that tells the hardware what to do.
On an FPGA you describe "what the hardware should look like" internally. It is as if you are making a chip specially made for your algorithm.
This speeds up a lot of things and can bring down the power consumption. But it has its ...
13
It depends a lot on the algorithm, but the principle can be explained quite simply.
Suppose that your algorithm has to sum a lot of 8-bit numbers. Your CPU will still need to fetch each instruction, get the operands from the RAM or the cache memory, execute the sum, store the result in cache, and go on with the next operation. The pipeline helps, but you ...
9
There are two ways of doing it.
1. Pin Planner
The first approach is in the Pin Planner tool. This is the GUI that allows you to select which pin goes where. From the main window with your project open, go to the Assignments menu and select Pin Planner (or press Ctrl+Shift+N).
In the pin planner window, in the All pins view at the bottom, right click on ...
7
A divider is a series of subtractions and multiplexers that select the value for the next step. If it is done purely combinatorially, then the critical path through all of this logic is quite long (even with carry lookahead on the subtractors) and the clock cycle must be very slow.
But the process is easy to pipeline, and the number of pipeline stages you ...
7
Without the code, you can only expect general advice.
However the most likely scenario is that the outputs don't actually depend on the inputs, so that optimisation eliminates all the logic in between them and hardwires the outputs to '1', '0' or 'Z'.
This can often be due to a mistake in your logic, or a reflection of the fact that you are trying out an ...
6
Just connect it up directly with a wire (you will see a little blob appear to show it is connected). Then, name the bus something like name[msb..lsb], and then name the wire name[whichbit]. That will tell Quartus to connect them because they both have the same name and tell it which bit it should connect to. You will get errors if you choose a whichbit which ...
6
There are roughly 3 levels of specialization of computing equipment:
CPU (like in your laptop) is the most generic of them all. It can do everything, but this versatility comes at a price of slow speed and high power consumption. CPU is programmed on the go, the instructions come from RAM. Programs for CPU are quick, cheap and easy to write and very easy to ...
6
Add this tcl expression...
set_global_assignment -name NUM_PARALLEL_PROCESSORS 4
... to either assignment_defaults.qdf or the .qsf file. Both should be in the project's directory. The .qdf file may need to be created.
5
Yes, FPGA can outperform modern CPU (like Intel i7) in some specyfic task, but there are easier and cheaper methods to improve neural network performance.
By cheaper - I mean total effort, not FPGA IC cost, but also very fast memory for FPGA (you would need it for neural network) and whole development process.
Use SSE - I've seen pretty simple neural ...
5
For primitives, absolutely no benefit performance wise. The only use is it means you don't need to create files with your own primitives in, but if you rely on the Altera ones then migrating to something from another manufacturer would be harder.
Some things like FIFOs may contain Altera specific inline timing constraints or other synthesis directives for ...
5
Use the "Netlist Viewers" in the "Tools"-menu. The RTL-Viewer creates a hierarchical expandable diagram. Layout can be horrible at times.
5
Seeing that you're using a Lite version of Quartus, maybe you don't actually are interested in Altera synthesis, but more in general Verilog analysis and clever code optimization.
You might want to have a look at Yosys, which supports generating the graphs I think you want, is free, much easier on your RAM and CPU than Quartus and frankly, produces better ...
5
I suspect the difference is due to the negative coefficient in the 2nd case (according to the order of your diagrams).
Because your multiplying coefficients are all powers of 2, your multiplies can all be done by simple bit selects. For example, assuming you're doing 16-bit math, x*0.25 can be calculated as simply {2'b0, x[15:2]} (using Verilog notation).
...
4
Your schematic shows a T-type flip-flop, which toggles when its input is high. Your rtl code, on the other hand, implements a regular D-type flip-flop. Your module should instead read:
always@(posedge clk, negedge clr)
begin
if(~clr)
q <= 1'b0;
else
q <= q ^ t;
end
By XOR'ing the output with the input, you will toggle the ...
4
You can use the memory IP cores to create a memory with initial mif content. You can check the IP core user guide for more information.
Another solution is to use VHDL attributes to initialize the content of your variable. You have to be confident that your code is indeed interpreted as a ROM by altera, otherwise the attribute will be ignored. This is the ...
4
It is not an 'error' to sample data from one clock domain in another. Quartus will not prevent you doing it at design entry/synthesis stage. When you later run timing analysis with quartus_sta you will find that the register path between the two clocks (if truly different) is unable to make timing.
You are running timing analysis, right?
4
The difference between the two is not that compilation broke your design, but rather the first case is an RTL simulation (i.e. everything is ideal), whereas the second case is a Gate-Level simulation, which factors in the propagation delays estimated for the actual real implementation.
Your circuit design works in the ideal case, however once you factor in ...
4
TL;DR; The answer may depend on the synthesis tools, but most likely the answer is no unless you use randomised seeds.
Certainly for modern versions of Intel/Altera Quartus (since some time before 12.1), if you compile the exact same source files using the exact same software version (including subversion/patch level) for the same device, you will get the ...
4
Your switches will be active low (i.e. zero when pressed).
Your LEDs will also be active low (i.e. zero will turn them on).
If you invert the inputs and output of an AND gate, you get an OR gate, hence the behaviour you are seeing.
There is nothing wrong with the FPGA.
4
Yes, there is "bouncing" — but in this context, we call them "glitches". The comparator (count > 26'd24999999) represents a rather large amount of combinatorial logic, and there's no chance that all paths through this logic (and the associated FPGA interconnect) will have exactly the same delay. Therefore, the output pulse will experience one or ...
4
Per the In-System Modificationof Memory and Constants.
When you specify that a memory or constant is run-time modifiable, the Quartus II software changes the default implementation. A single-port RAM is converted to a dual-port RAM, and a constant is implemented in registers instead of look-up tables (LUTs). These changes enable run-time modification ...
3
you check the warnings when you are compiling your code. Mostly synthesis issuses can be solved if you correct those warnings.
3
The question doesn't contain near enough detail, so I'm mostly making assumptions here...
Carry in is an input. I suspect you stop driving the carry-in input (so it "floats") when you switch to addition mode.
There is a good discussion of this issue here.
3
I usually synchronise my async reset through a delay line of a few flipflops (relying on the FPGA configuration to have cleared them), and only use that synchronised reset (even if I'm using it as an asynchronous reset).
In Xilinx-land, the tools can trace the timing through from the clock used in the delay line to the reset input (either sync or async) ...
3
Metastability? Highly unlikely.
Unsynchronised inputs? Very probable and they can cause the symptoms you describe.
So clock each SPI input from your fast clock, and route the clocked versions to the SPI core. (Unless you're already certain that it reclocks them already).
3
I would like to point out that the weak pullup resistors on an FPGA/SOC/MCU are not a replacement for real external pullups. So when devising a strategy to use it please take the following into account.
On-chip weak pullups are primarily for use when pins are left unused in a design and the pads do not have anything connected in the board etch artwork.
The ...
3
Within the qsf file, you can add the following:
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to pin_name
3
A safe state machine in Quartus is a state machine that if it reaches an illegal state (for any exceptional reason, such as glitch, metastability, etc.), it will reach the reset state after one clock cycle.
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