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37 votes

Why do FPGA projects always take the same amount of time to compile?

With software ... if we change a single file in the project, everything does not need to be compiled again. Only if your compilation creates intermediate files to avoid recompiling unchanged files. ...
Tom Carpenter's user avatar
21 votes
Accepted

FPGA starts working after irrelevant changes, why?

Your uart_rx signal is asynchronous to your clock. However, you have one place in your code where you use it directly in the state machine. This is curious, because ...
Dave Tweed's user avatar
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21 votes

Why do FPGA projects always take the same amount of time to compile?

This is because of how the FPGA toolchain works. There are several main steps: synthesis, mapping, placement, and routing. Synthesis is the only one that is similar to compilation. Synthesis is ...
alex.forencich's user avatar
18 votes

Is using floor plan tool during FPGA design ever actually useful or required?

Since nobody has answered, here are a few things you can do in the floorplanner (my experience is with Xilinx tools, but I expect the others are similar): Verify "visually" that some ...
The Photon's user avatar
  • 129k
16 votes

Why do FPGA projects always take the same amount of time to compile?

Because in software, there is a linking phase. The linker takes all objects files (resulting from the compilation of each source files), and only alter the function calls so that everything works ...
dim's user avatar
  • 16k
14 votes

Quartus Can't fit design into Device, is there any way to optimize it to get it to fit?

I'm afraid you're making a classic Verilog/VHDL mistake: trying to write a computer program in an HDL, instead of using it to design a digital logic circuit. An FPGA has no CPU to run Verilog 'lines' ...
TonyM's user avatar
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12 votes
Accepted

Altera FPGA I/O weak pull ups

There are two ways of doing it. 1. Pin Planner The first approach is in the Pin Planner tool. This is the GUI that allows you to select which pin goes where. From the main window with your project ...
Tom Carpenter's user avatar
10 votes
Accepted

Altera Quartus "Warning (18236): Number of processors has not been specified...", how to suppress?

Add this tcl expression... set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL ... to either assignment_defaults.qdf or the .qsf file. Both should be in the ...
JimFred's user avatar
  • 703
10 votes
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Is using floor plan tool during FPGA design ever actually useful or required?

Why would one ever need to use these floor plan tools to lock design logic into specific regions? Is there any benefit to doing this? Is this ever really required? There are certainly reasons why it ...
Tom Carpenter's user avatar
9 votes
Accepted

UART receiving random values

The problem is sending constant data stream without any pauses between symbols. The ASCII symbol 'S' has a value of 0x53, so it is sent over the wire as repeating pattern of 0110010101 which includes ...
Justme's user avatar
  • 143k
8 votes

Why do FPGA projects always take the same amount of time to compile?

NOTE (not explicit in other answers): FPGA build tools and software build tools both have to fit the end-product into a space. For software it's a logical address space, and the spatial relationship ...
Solomon Slow's user avatar
  • 3,053
8 votes

Is using floor plan tool during FPGA design ever actually useful or required?

The other answers already give several important points and I'll add another: When you work in a safety critical environment, you might want to spatially separate functions in order to harden them ...
njg's user avatar
  • 103
8 votes

Is there any way to know how real discrete components are being connected to each other using logical gates?

When you design in an HDL, you are not actually designing circuits. You are designing logic. Another program (typically) then takes this logic and performs the circuit synthesis based on your target ...
DELTA12's user avatar
  • 778
7 votes
Accepted

How do I generate a schematic block diagram from Verilog with Quartus Prime?

Use the "Netlist Viewers" in the "Tools"-menu. The RTL-Viewer creates a hierarchical expandable diagram. Layout can be horrible at times.
Andreas's user avatar
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7 votes

Is using floor plan tool during FPGA design ever actually useful or required?

Yes, it is very useful for a number of things, mainly to get insight into what the tools did with your design. It's especially useful when working on timing closure. From the floorplan, you can ...
alex.forencich's user avatar
6 votes
Accepted

Bus to wire in quartus

Just connect it up directly with a wire (you will see a little blob appear to show it is connected). Then, name the bus something like name[msb..lsb], and then name ...
Tom Carpenter's user avatar
6 votes

How do I generate a schematic block diagram from Verilog with Quartus Prime?

Seeing that you're using a Lite version of Quartus, maybe you don't actually are interested in Altera synthesis, but more in general Verilog analysis and clever code optimization. You might want to ...
Marcus Müller's user avatar
6 votes

Why do FPGA projects always take the same amount of time to compile?

I have used incremental FPGA compile in the distant past without any design partition, but IIRC it failed every 1 in 2 or 3 attempts and I ended up doing a full compile anyway. However, if you have a ...
David Omar's user avatar
6 votes

Help me debug these VHDL errors please

This is not specific to VHDL, but generally here's how to interpret compiler error messages: Error (10500): VHDL syntax error at clothes_washer.vhd(22) near text ")"; expecting an ...
MarkU's user avatar
  • 14.6k
6 votes

Quartus Can't fit design into Device, is there any way to optimize it to get it to fit?

A running average can be implemented with just the buffer, one register, an adder and a subtractor. It doesn't need to take many resources. Image credit - https://surf-vhdl.com/how-to-implement-...
Kevin White's user avatar
  • 32.9k
5 votes

Altera FPGA I/O weak pull ups

I would like to point out that the weak pullup resistors on an FPGA/SOC/MCU are not a replacement for real external pullups. So when devising a strategy to use it please take the following into ...
Michael Karas's user avatar
5 votes

FPGA maximum frequency : limiting factor

I suspect the difference is due to the negative coefficient in the 2nd case (according to the order of your diagrams). Because your multiplying coefficients are all powers of 2, your multiplies can ...
The Photon's user avatar
  • 129k
5 votes
Accepted

Why can't dual port RAM be read out using the Quartus In-System Memory Content Editor?

Per the In-System Modificationof Memory and Constants. When you specify that a memory or constant is run-time modifiable, the Quartus II software changes the default implementation. A single-port ...
Tom Carpenter's user avatar
5 votes

UART receiving random values

As an addition to Justmes answer (feel free to combine this into your answer): This is a UART Transmission of an S: This is what happens if you dont have an idle: And this part is what the receiver ...
BeB00's user avatar
  • 5,435
4 votes
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8 bit counter from T Flip Flops

Your schematic shows a T-type flip-flop, which toggles when its input is high. Your rtl code, on the other hand, implements a regular D-type flip-flop. Your module should instead read: ...
Scott Teal's user avatar
4 votes

Altera FPGA I/O weak pull ups

Within the qsf file, you can add the following: set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to pin_name
Chris Cornish's user avatar
4 votes
Accepted

What is a safe state machine?

A safe state machine in Quartus is a state machine that if it reaches an illegal state (for any exceptional reason, such as glitch, metastability, etc.), it will reach the reset state after one clock ...
Claudio Avi Chami's user avatar
4 votes
Accepted

VHDL to RTL/schematic, not what I expect to see

Quartus is synthesizing a separate mux for each bit of your output vector. The eight inputs to each mux are bit \$N\$ from each of the eight inputs. The output of each mux is bit \$N\$ of the output. ...
Elliot Alderson's user avatar
4 votes
Accepted

74193 stops working after compilation on another PC (QUARTUS)

The difference between the two is not that compilation broke your design, but rather the first case is an RTL simulation (i.e. everything is ideal), whereas the second case is a Gate-Level simulation, ...
Tom Carpenter's user avatar
4 votes
Accepted

Inherent Pseudo-Randomness in modern FPGA design tools

TL;DR; The answer may depend on the synthesis tools, but most likely the answer is no unless you use randomised seeds. Certainly for modern versions of Intel/Altera Quartus (since some time before 12....
Tom Carpenter's user avatar

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