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36

With software ... if we change a single file in the project, everything does not need to be compiled again. Only if your compilation creates intermediate files to avoid recompiling unchanged files. FPGAs ... It should take less time to compile after the first time isn't it? In an FPGA compile, unless you are using incremental compilation (which is a ...


25

A colleague of mine benchmarked this and came to the conclusion that FPGAs would outperform a PC once you had more than about 100 independent, integer tasks that would fit in the FPGA. For floating point tasks GPGPU beat FPGA throughout. For narrow multithreading or SIMD operation then CPUs are extremely optimised and run at a higher clock speed than FPGAs ...


21

Your uart_rx signal is asynchronous to your clock. However, you have one place in your code where you use it directly in the state machine. This is curious, because in all other cases, you are careful to assign it to rx1 and then test that. IDLERX: begin rx_bitcount <= 4'd0; rx_busy <= 1'b0; if (uart_rx == 1'b0 && rx_err !...


19

An FPGA works completely differently from a processor. For a processor you write software that tells the hardware what to do. On an FPGA you describe "what the hardware should look like" internally. It is as if you are making a chip specially made for your algorithm. This speeds up a lot of things and can bring down the power consumption. But it has its ...


19

This is because of how the FPGA toolchain works. There are several main steps: synthesis, mapping, placement, and routing. Synthesis is the only one that is similar to compilation. Synthesis is also the only step that is easiest to parallelize (each module can be synthesized independently of the other modules) and as a result it is usually only a small ...


18

Since nobody has answered, here are a few things you can do in the floorplanner (my experience is with Xilinx tools, but I expect the others are similar): Verify "visually" that some particular resources have been used. For example carry chains, block RAMs, clock management tiles, etc. Verify that highly interconnected logical functions have been ...


15

Because in software, there is a linking phase. The linker takes all objects files (resulting from the compilation of each source files), and only alter the function calls so that everything works together. The linker has a rather simple job, and does not have to go through the process of generating code from the source, and optimizing everything (which is ...


13

It depends a lot on the algorithm, but the principle can be explained quite simply. Suppose that your algorithm has to sum a lot of 8-bit numbers. Your CPU will still need to fetch each instruction, get the operands from the RAM or the cache memory, execute the sum, store the result in cache, and go on with the next operation. The pipeline helps, but you ...


10

There are two ways of doing it. 1. Pin Planner The first approach is in the Pin Planner tool. This is the GUI that allows you to select which pin goes where. From the main window with your project open, go to the Assignments menu and select Pin Planner (or press Ctrl+Shift+N). In the pin planner window, in the All pins view at the bottom, right click on any ...


10

Why would one ever need to use these floor plan tools to lock design logic into specific regions? Is there any benefit to doing this? Is this ever really required? There are certainly reasons why it is useful, but it really depends on the design. For massively interconnected designs which don't have nice groupings (e.g. there are lots of processing cores ...


9

The problem is sending constant data stream without any pauses between symbols. The ASCII symbol 'S' has a value of 0x53, so it is sent over the wire as repeating pattern of 0110010101 which includes the start and stop bits. Because there is no pauses between transmissions, the receiving UART does not know which bits are the start and stop bits in the ...


8

NOTE (not explicit in other answers): FPGA build tools and software build tools both have to fit the end-product into a space. For software it's a logical address space, and the spatial relationship of one subroutine to another is completely irrelevant to how they interact. But, for an FPGA, it's a physical space. And the spatial relationships beteween ...


8

The other answers already give several important points and I'll add another: When you work in a safety critical environment, you might want to spatially separate functions in order to harden them against single event upsets (SEUs) (such as triplicating the functionality and then majority vote the results). There are several ways of doing this like ...


7

A divider is a series of subtractions and multiplexers that select the value for the next step. If it is done purely combinatorially, then the critical path through all of this logic is quite long (even with carry lookahead on the subtractors) and the clock cycle must be very slow. But the process is easy to pipeline, and the number of pipeline stages you ...


7

Add this tcl expression... set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL ... to either assignment_defaults.qdf or the .qsf file. Both should be in the project's directory. The .qdf file may need to be created.


7

Yes, it is very useful for a number of things, mainly to get insight into what the tools did with your design. It's especially useful when working on timing closure. From the floorplan, you can usually highlight different components in the design and see how much area they take up and what they are physically located adjacent to. This can indicate if the ...


6

Just connect it up directly with a wire (you will see a little blob appear to show it is connected). Then, name the bus something like name[msb..lsb], and then name the wire name[whichbit]. That will tell Quartus to connect them because they both have the same name and tell it which bit it should connect to. You will get errors if you choose a whichbit which ...


6

There are roughly 3 levels of specialization of computing equipment: CPU (like in your laptop) is the most generic of them all. It can do everything, but this versatility comes at a price of slow speed and high power consumption. CPU is programmed on the go, the instructions come from RAM. Programs for CPU are quick, cheap and easy to write and very easy to ...


6

Use the "Netlist Viewers" in the "Tools"-menu. The RTL-Viewer creates a hierarchical expandable diagram. Layout can be horrible at times.


6

Seeing that you're using a Lite version of Quartus, maybe you don't actually are interested in Altera synthesis, but more in general Verilog analysis and clever code optimization. You might want to have a look at Yosys, which supports generating the graphs I think you want, is free, much easier on your RAM and CPU than Quartus and frankly, produces better ...


6

I have used incremental FPGA compile in the distant past without any design partition, but IIRC it failed every 1 in 2 or 3 attempts and I ended up doing a full compile anyway. However, if you have a large design and you want to cut the overall compile time, there are some tricks that you could try. They are not trivial, and not quick to implement, so you ...


6

This is not specific to VHDL, but generally here's how to interpret compiler error messages: Error (10500): VHDL syntax error at clothes_washer.vhd(22) near text ")"; expecting an identifier, or "constant", or "file", or "signal", or "variable" The keyword "Error" means a serious problem that ...


5

Yes, FPGA can outperform modern CPU (like Intel i7) in some specyfic task, but there are easier and cheaper methods to improve neural network performance. By cheaper - I mean total effort, not FPGA IC cost, but also very fast memory for FPGA (you would need it for neural network) and whole development process. Use SSE - I've seen pretty simple neural ...


5

For primitives, absolutely no benefit performance wise. The only use is it means you don't need to create files with your own primitives in, but if you rely on the Altera ones then migrating to something from another manufacturer would be harder. Some things like FIFOs may contain Altera specific inline timing constraints or other synthesis directives for ...


5

I suspect the difference is due to the negative coefficient in the 2nd case (according to the order of your diagrams). Because your multiplying coefficients are all powers of 2, your multiplies can all be done by simple bit selects. For example, assuming you're doing 16-bit math, x*0.25 can be calculated as simply {2'b0, x[15:2]} (using Verilog notation). ...


5

As an addition to Justmes answer (feel free to combine this into your answer): This is a UART Transmission of an S: This is what happens if you dont have an idle: And this part is what the receiver sees as a repeating 0xAA: edit: to be clear, i dont think this should be marked as the answer. This should just be an addendum to Justme's answer


4

I would like to point out that the weak pullup resistors on an FPGA/SOC/MCU are not a replacement for real external pullups. So when devising a strategy to use it please take the following into account. On-chip weak pullups are primarily for use when pins are left unused in a design and the pads do not have anything connected in the board etch artwork. The ...


4

You can use the memory IP cores to create a memory with initial mif content. You can check the IP core user guide for more information. Another solution is to use VHDL attributes to initialize the content of your variable. You have to be confident that your code is indeed interpreted as a ROM by altera, otherwise the attribute will be ignored. This is the ...


4

Your schematic shows a T-type flip-flop, which toggles when its input is high. Your rtl code, on the other hand, implements a regular D-type flip-flop. Your module should instead read: always@(posedge clk, negedge clr) begin if(~clr) q <= 1'b0; else q <= q ^ t; end By XOR'ing the output with the input, you will toggle the ...


4

A safe state machine in Quartus is a state machine that if it reaches an illegal state (for any exceptional reason, such as glitch, metastability, etc.), it will reach the reset state after one clock cycle.


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