4

Generics and constant values can be seen in the objects window of QuestaSim/ModelSim. You could also drag them into the waveform, but they wont change ... (clickable)


4

Just in case the comments weren't clear: the warning means that you cannot use more than one choice in an array aggregate if you're using a non-static value (a generic or something derived from a generic) to define the ranges or positions. I don't know, however, why the restriction exists. There is a simple workaround to defining such constants. Just break ...


3

Even floating point numbers have limits. 9.5e+500 is outside the limits of binary64 (4.9e-324 to 1.8e+308), which is what real implements. As for why it's complaining about "32-bit capacity", that I couldn't tell you. Might be a compiler bug.


2

It isn't telling you that you're missing any parentheses; it's telling you that it isn't expecting a parenthesis at all in that spot. You didn't provide any context, but if your assert is outside a procedural block (initial or always), then a property name must appear between the assert and the (. This is known as an "concurrent assert". The other type (...


1

You want a user defined radix. For example radix define States { 11'b00000000001 "IDLE", 11'b00000000010 "CTRL", 11'b00000000100 "WT_WD_1", 11'b00000001000 "WT_WD_2", 11'b00000010000 "WT_BLK_1", 11'b00000100000 "WT_BLK_2", 11'b00001000000 "WT_BLK_3", 11'b00010000000 "WT_BLK_4", 11'b00100000000 "WT_BLK_5", 11'b01000000000 "RD_WD_1", 11'b10000000000 "RD_WD_2",...


1

Wish I could comment, b/c there are a lot of syntactical issues here. You defined a type called H and then tried to assign something to the type: H(0) := v_adcValue which is illegal and may explain the first part of the error. You must define the type and then declare a variable or signal of the defined type, which can then receive assignment. It looks ...


1

The -sv_seed random is an option the to vsim command line. By the time you get to vsim's transcript window, it's too late to change the seed. When invoking Questa from the shell command vsim -sv_seed random ... When starting Questa simulation using the GUI, look for form to fill in vsim options.


1

First check if there are options to vcom which accomplish what you want. Then see (at least on a unix-like system) if it is segregating output between stdout and stderr in any useful way. In desperation, on a unix-like system a technique you can use to solve this type of problem for just about any command-line tool is to combine the two output streams and ...


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