Hot answers tagged

67

See this extremely detailed account of the PC boot sequence: http://www.drdobbs.com/parallel/booting-an-intel-architecture-system-par/232300699?pgno=2 Since no DRAM is available at this point, code initially operates in a stackless environment. Most modern processors have an internal cache that can be configured as RAM to provide a software stack. ...


60

It seems like you're referring specifically to http://www.nature.com/nphoton/journal/v8/n11/full/nphoton.2014.243.html . It can be read here: https://www.researchgate.net/publication/269099858_Ultra-high-density_spatial_division_multiplexing_with_a_few-mode_multicore_fibre . In this case, it's slightly more complicated than "an optical signal". The link ...


44

There are several reasons for this. First of all, memory takes up a lot of silicon area. This means that increasing the amount of RAM directly increases the silicon area of the chip and hence the cost. Larger silicon area has a 'double whammy' effect on price: larger chips mean less chips per wafer, especially around the edge, and larger chips means each ...


44

Short answer: You might be able to "connect a battery to a RAM to prevent data loss during power outage", but this depends on the type of RAM. SRAM (Static Random Access Memory) is not DRAM, explained below. SRAMs are found in many electronic devices such as a modern (home) thermostat (uses a battery to retain the settings if the power goes out) and in an ...


43

Rather than worrying about a research paper that's pushing things to the limit first start by understanding the stuff sitting in front of you. How does an SATA 3 hard drive in a home computer put 6 Gbits/s down a serial link? The main processor isn't 6 GHz and the one in the hard drive certainly isn't so by your logic it shouldn't be possible. The answer ...


34

It's because it's easier and cheaper to increase the bandwidth of the DRAM than to decrease the latency. To get the data from an open row of ram, a non trivial amount of work is necessary. The column address needs to be decoded, the muxes selecting which lines to access need to be driven, and the data needs to move across the chip to the output buffers. ...


33

With SDR, there are two clock edges per bit, but only at most one edge on the data line. With high frequency communication, the analog bandwidth limits how close you can put edges together on any given wire. If your clock signal hits that limit, you're wasting half of the bandwidth of the data wires. Therefore, DDR was invented so that all of the wires hit ...


32

In addition to the speed & other features which others have already mentioned, executing code from RAM can be useful in bootloaders where you need to reprogram your micro's flash - you can't execute code from flash which you're in the middle of erasing & reprogramming.


31

The board is a multi-layer stackup, probably 4-layer. This means that there are more layers inside the PCB on which other connections are routed. You can tell this from the seemingly disappearing routing, but also from the colour of the board. Notice how it is light around the edges (where light can shine through), but then suddenly gets dark. The dark ...


23

Can we not simply connect a battery to a RAM to prevent data loss during power cuts? So can you tell me why is this not done? Of course we do! It's called battery-backed SRAM, and it's widely used in embedded systems. These days, the cost of NVRAM technology (such as conventional EEPROM, or new FRAM) is low, they can do the same thing without power, so it's ...


20

If there is a single memory interface, there would be hardware to arbitrate between requests. Typically a processor would be given priority over I/O without starving I/O, but even with I/O always having priority the processor would have some opportunities to access memory because I/O tends to have lower bandwidth demands and to be intermittent. In addition, ...


20

No, there is no minimum frequency because it's static RAM. Any digital circuit that's described as "static" doesn't have a minimum frequency - it can operate with all signals held static for an extended period of time, hence the name. "Dynamic" circuits have a minimum frequency. Just because your circuit operates at a low frequency doesn't mean you can ...


19

The PCB most probalby has 4 layers. The outer 2 which you can see are used to carry the signals and the inner 2 are power layers - 1 for ground and 1 for Vcc. This is the most common approach when designing digital electronics. Inner layers can be seen as the dark regions inside the board. Vias - a small copper plated holes are used to conduct between ...


19

I didn't look at the datasheet for that micro. However, it is often the case in this situation that fetching from RAM is faster than fetching from the flash the program memory is implemented from. The advantage of flash is that large amounts can be relatively cheap. Microcontroller manufacturers therefore sometimes put a lot of flash on a chip, then ...


19

The real problem is bandwidth. The highest frequency that a data line can generate (well, not counting slew rate) is when it's sending a 101010 data pattern, which occurs at half of the data rate. With single data rate (SDR) transmission, the clock produces one complete cycle for each data bit, hence running at double the frequency of what you might see on a ...


18

You are correct that the CPU cannot be accessing the memory during a DMA transfer. However there are two factors which in combination allow apparent parallel memory access by the CPU and the device performing the DMA transfer: The CPU takes multiple clock cycles to execute an instruction. Once it has fetched the instruction, which takes maybe one or two ...


17

When you want to execute in RAM because it is faster, it's usually because that RAM is on-chip SRAM. This is a scarce resource, which you will probably want for data that requires read/write access. Using it for code when you already have the code in ROM/flash means that you need X amount of flash and an additional X amount of RAM. It also requires an ...


16

The datasheet should tell you how long each instruction takes, and what differences there are, if any, between executing from RAM or ROM. For microcontroller that offer the option of executing from RAM, that is probably faster, likely being the main point of using additional RAM space to execute code from. There may also be some fetch overlap issues. In ...


15

Memory probably takes up the most silicon space, and RAM being very fast to use is volatile - and uses power constantly to keep its state. Unless you need lots of RAM, it's not useful for many other applications. If an embedded system designer needs more RAM, they merely get an external RAM chip and use peripheral memory interfaces that microcontrollers ...


15

Ignoring the details of the specific transmission in question (which @alex.forencich has already discussed in considerable detail), it seems like it's probably useful to consider the more general case. Although this particular transmission hit 255 Tbps through the fiber, extremely fast fiber links are already in regular use. I'm not sure exactly how many ...


14

These "hardware addressing" pins are not for addressing words in the RAM, but rather to select the address of the whole device on the IIC bus. The manufacturer realizes that you might want to have several of these chips on the same IIC bus, which means they each need a different IIC bus address. These pins allow you to pick one of 8 pre-defined addresses ...


14

Besides the excellent points brought up in the other answers, another reason for limited RAM is the architecture of the microcontroller. For example, take the the Microchip PIC10LF320, which has only 448 bytes of program (flash) memory and 64 bytes of RAM. But it probably costs only 25ȼ (or less) in large quantities. The limited size of the PIC10 ...


14

In general the stack and the heap crash in to each other. At that point it all gets messy. Depending on the MCU one of several things may (or will) happen. Variables get corrupted The stack gets corrupted The program gets corrupted When 1 happens you start getting strange behaviour - things not doing what they should. When 2 happens all manner of hell ...


14

When the 1MB of memory is referred to, do the books refer to the ROM and RAM of the computer. Is the ROM + RAM = 1MB of memory interfaced? Correct. The CPU does not distinguish between RAM and ROM; the 1 MB address space is shared between both. If yes, when memory mapped I/O is shown as a memory segment in this 1MB memory space.....do they mean that the ...


14

Generally, the cache memory is not addressable. A program cannot store or retrieve data intentionally from it.


14

In addition to all good answers: Why wouldn't I just always execute from RAM if the benefit is only increased speed? Because in an embedded system, usually you don't have the required amount of RAM. For example a STM32 having 32kB or RAM and 512kB of EEPROM. To be able to execute entire program in RAM you would need a RAM size bigger than EEPROM.


13

This depends on the device. RAM can be built faster than Flash; this starts to become important in about the 100MHz range. Simple microcontrollers Small slow microcontrollers execute directly out of Flash. These systems usually have more Flash than SRAM too. Midrange systems Once your device gets faster then the situation is a little different. Midrange ...


13

Other answers don't seem to have discussed power consumption much, which you specifically asked about. The answer is that it depends somewhat on the microcontroller, but often execution from RAM can reduce power consumption because it requires less energy to read instructions from RAM than from flash memory. A typical use would be to run a low power "sleep"...


12

An alternative view : Microcontrollers don't run out of memory. At least, not when programmed properly. Programming a microcontroller is not exactly like general purpose programming, to do it properly you have to be aware of its constraints and program accordingly. There are tools to help ensure this. Search them out and learn them - at least how to read ...


12

DRAM is built as a capacitor and a switch for each bit - the data is stored as a charge on the capacitor. It is pretty much impossible to make a perfect capacitor and a perfect transistor, certainly not on the tiny scale used in DRAM chips. There are leakage currents within the system - between the capacitor plates, across the channel of the transistor, etc....


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