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69 votes

Can a CPU function with nothing more than a power supply and a ROM, using only the internal cache as RAM?

See this extremely detailed account of the PC boot sequence: http://www.drdobbs.com/parallel/booting-an-intel-architecture-system-par/232300699?pgno=2 Since no DRAM is available at this point, code ...
pjc50's user avatar
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60 votes

How is 255 Tbit/s processed in optical fiber communication?

It seems like you're referring specifically to http://www.nature.com/nphoton/journal/v8/n11/full/nphoton.2014.243.html . It can be read here: https://www.researchgate.net/publication/269099858_Ultra-...
alex.forencich's user avatar
48 votes
Accepted

Can we not simply connect a battery to a RAM to prevent data loss during power cuts?

Short answer: You might be able to "connect a battery to a RAM to prevent data loss during power outage", but this depends on the type of RAM. SRAM (Static Random Access Memory) is not DRAM, ...
rdtsc's user avatar
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43 votes
Accepted

How is 255 Tbit/s processed in optical fiber communication?

Rather than worrying about a research paper that's pushing things to the limit first start by understanding the stuff sitting in front of you. How does an SATA 3 hard drive in a home computer put 6 ...
Andrew's user avatar
  • 6,912
36 votes
Accepted

Why use DDR instead of increasing clock speed?

With SDR, there are two clock edges per bit, but only at most one edge on the data line. With high frequency communication, the analog bandwidth limits how close you can put edges together on any ...
Dave Tweed's user avatar
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34 votes
Accepted

Why does RAM (any type) access time decrease so slowly?

It's because it's easier and cheaper to increase the bandwidth of the DRAM than to decrease the latency. To get the data from an open row of ram, a non trivial amount of work is necessary. The ...
C_Elegans's user avatar
  • 2,901
33 votes

Why execute code from RAM?

In addition to the speed & other features which others have already mentioned, executing code from RAM can be useful in bootloaders where you need to reprogram your micro's flash - you can't ...
brhans's user avatar
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31 votes
Accepted

72-pin SIMM RAM: how do ground (Vss) and supply (Vcc) voltage pins work

The board is a multi-layer stackup, probably 4-layer. This means that there are more layers inside the PCB on which other connections are routed. You can tell this from the seemingly disappearing ...
Tom Carpenter's user avatar
25 votes

Can we not simply connect a battery to a RAM to prevent data loss during power cuts?

Can we not simply connect a battery to a RAM to prevent data loss during power cuts? So can you tell me why is this not done? Of course we do! It's called battery-backed SRAM, and it's widely used in ...
比尔盖子's user avatar
  • 7,218
25 votes
Accepted

Enable vendor-disabled hardware on tablet?

Each of those modules is 4Gb (Gigabit). So you have 8Gb of RAM. A byte is typically 8-bits, so that equates to 1GB of RAM, which is what your OS is reporting. There is no disabled memory that you can ...
Tom Carpenter's user avatar
23 votes
Accepted

How can I access more than 15 addresses of data from my 8 bit incomplete computer?

the half of the byte in memory is the opcode and other half is the address Well, that's one way of doing it, but there are lots of ways of doing it. Instructions don't have to contain the address. ...
pjc50's user avatar
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20 votes

Is there a lower limit on operating frequency of CMOS SRAM?

No, there is no minimum frequency because it's static RAM. Any digital circuit that's described as "static" doesn't have a minimum frequency - it can operate with all signals held static for an ...
Jonathan S.'s user avatar
19 votes

72-pin SIMM RAM: how do ground (Vss) and supply (Vcc) voltage pins work

The PCB most probalby has 4 layers. The outer 2 which you can see are used to carry the signals and the inner 2 are power layers - 1 for ground and 1 for Vcc. This is the most common approach when ...
Todor Simeonov's user avatar
19 votes

Why execute code from RAM?

When you want to execute in RAM because it is faster, it's usually because that RAM is on-chip SRAM. This is a scarce resource, which you will probably want for data that requires read/write access. ...
pipe's user avatar
  • 14.5k
19 votes

Why execute code from RAM?

I didn't look at the datasheet for that micro. However, it is often the case in this situation that fetching from RAM is faster than fetching from the flash the program memory is implemented from. ...
Olin Lathrop's user avatar
19 votes

Why use DDR instead of increasing clock speed?

The real problem is bandwidth. The highest frequency that a data line can generate (well, not counting slew rate) is when it's sending a 101010 data pattern, which occurs at half of the data rate. ...
alex.forencich's user avatar
15 votes

How is 255 Tbit/s processed in optical fiber communication?

Ignoring the details of the specific transmission in question (which @alex.forencich has already discussed in considerable detail), it seems like it's probably useful to consider the more general case....
Jerry Coffin's user avatar
  • 3,514
14 votes

Can a CPU function with nothing more than a power supply and a ROM, using only the internal cache as RAM?

Generally, the cache memory is not addressable. A program cannot store or retrieve data intentionally from it.
Lior Bilia's user avatar
  • 7,600
14 votes

Why execute code from RAM?

In addition to all good answers: Why wouldn't I just always execute from RAM if the benefit is only increased speed? Because in an embedded system, usually you don't have the required amount of ...
Marko Buršič's user avatar
13 votes

Why execute code from RAM?

Other answers don't seem to have discussed power consumption much, which you specifically asked about. The answer is that it depends somewhat on the microcontroller, but often execution from RAM can ...
user's user avatar
  • 1,901
12 votes

EEPROM with high endurance

Another solution could be to use a microcontroller with non-volatile FRAM. FRAM doesn't suffer from the same limitations on write cycles as EEPROM. Some of the MSP430 products from TI are available ...
John D's user avatar
  • 24.1k
12 votes
Accepted

Why is this clock signal connected to a capacitor to gnd?

C7 and R58 form a high pass filter, also known as a differentiator. The purpose of using a differentiator in this spot is to cause a short pulse on the rising and falling edge of the clock signal. ...
JRE's user avatar
  • 72.4k
12 votes

Why is this clock signal connected to a capacitor to gnd?

The circuit overall is a 16-byte memory bank for a homebrew computer of some sort, with manual programming capability via the switches and lights. Probably the most complicated 16 bytes of memory you'...
Dave Tweed's user avatar
  • 175k
11 votes

EEPROM with high endurance

I have this issue in a current project. The way I'm dealing with it is to keep the live value of the counter in RAM. I added a little bit of hardware so that the microcontroller can detect that the ...
Olin Lathrop's user avatar
11 votes

How do I find out at compile time how much of an STM32's Flash memory and dynamic memory (SRAM) is used up?

If you want a quick Linux bash script to auto-calculate Flash and SRAM usage for you, see my other answer here. TLDR Jump straight down to the "Summary" at the bottom. Details: @duskwuff -...
Gabriel Staples's user avatar
11 votes
Accepted

How is a memory location accessed by random access?

Figure 1. An 8-bit wide random access memory. Image source: ETSU. Steps: Select the address to be read. This is binary coded and fed into the memory address decoder. The address decoder selects one ...
Transistor's user avatar
  • 177k
11 votes
Accepted

What is the theoretical maximum capacity of 72-pin RAM modules?

Did you look at the functional block diagrams in that datasheet? The four CAS# lines are used to enable the four bytes of a 32-bit word.1 Furthermore, two RAS# lines are used for each 32-bit word. ...
Dave Tweed's user avatar
  • 175k
10 votes
Accepted

Is this BRAM being fully utilized if I use a different data width?

Correct, the remaining bits are unused. This is something you just have to accept in FPGAs, you are never going to use all of the resources. It's the price you pay for configurability. On the plus ...
Tom Carpenter's user avatar

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