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44

Short answer: You might be able to "connect a battery to a RAM to prevent data loss during power outage", but this depends on the type of RAM. SRAM (Static Random Access Memory) is not DRAM, explained below. SRAMs are found in many electronic devices such as a modern (home) thermostat (uses a battery to retain the settings if the power goes out) and in an ...


23

Can we not simply connect a battery to a RAM to prevent data loss during power cuts? So can you tell me why is this not done? Of course we do! It's called battery-backed SRAM, and it's widely used in embedded systems. These days, the cost of NVRAM technology (such as conventional EEPROM, or new FRAM) is low, they can do the same thing without power, so it's ...


7

For a PC, that's more or less what "hibernate on low battery" is. The contents of RAM are written to disk in the hibernation file. Since you need the whole system to be on while doing this, it needs quite a lot of power, and is therefore only suitable for systems which would have a battery anyway like laptops. Similarly it's possible to boot quickly from ...


6

In general: There are many ways and it's not trivial. You will need to design something yourself. If the amount of data is very small (like controller inputs) you could use a register which stores the latest data. The input side of the register connects (somehow - you'll need to design some logic) to the interface CPU's memory bus, and the output side ...


6

EEPROM - because I guess HDDs and SDDs consume more power. SSDs are EEPROM by definition. What you describe is exactly how "suspend to disk" or "hibernate" functions in modern computers do. You pull the plug, the battery or an external battery (UPS) starts to power the computer and when the battery depletes to a certain point, the OS (depending on ...


5

Single-event upsets (SEU) at sea level tend to be caused either by radioactive contaminants in the IC manufacturing materials (particularly the metals) generating alpha particles or by high-energy neutrons (caused by cosmic rays in the atmosphere) ionizing atoms in the silicon itself. Over the years, manufacturers have greatly reduced the threat caused by ...


5

I love Python. Most of the programs I write for my own use on my PC at home are written in Python. That said, I don't use Python in my microcontroller based projects. Python is intended for use where you have memory and processor horsepower behind it. It dynamically allocates memory, and takes care of cleaning up objects your program doesn't need ...


4

Per the In-System Modificationof Memory and Constants. When you specify that a memory or constant is run-time modifiable, the Quartus II software changes the default implementation. A single-port RAM is converted to a dual-port RAM, and a constant is implemented in registers instead of look-up tables (LUTs). These changes enable run-time modification ...


3

Upper and lower byte enables are needed when a processor with a 16-bit bus wants to do an açcess to modify just one half of the data RAM location. For byte write operations this greatly increases performance over having to do a 16-bit read-modify-write operation.


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I also don't know for sure (those who know for sure are likely dead now.) But I'll take a shot. The 7489 was an early TTL memory device. Tri-state output wasn't available. Since it was also a big advantage to be able to wire-AND without additional output buffering, open-collector outputs was the obvious choice for devices that might have to share a bus. As ...


2

The answer is, more work needs to be done, and they aren't sure: The results show that the radiation susceptibility has actually improved somewhat for devices that have advanced to the 0.13μm level, which contradicts earlier predictions. This trend is encouraging, but it may not necessarily continue for devices that are scaled below 0.1 μm. It is ...


2

if I would replace a NOR Flash in a system with a NAND Flash that contains the same data Trouble is that you usually cannot get a NAND and a NOR flash with the same data interface or protocol. In other words, the existing system won't know how to access the new chip properly. And you really don't want to talk to raw flash directly, as e.g. SD cards are ...


2

To add to the other thorough answers, let me point out that simply having power available for the memory is insufficient to guarantee a proper restart where you left off. If you simply allow the power to drift out of specification for the processor it will typically "go nuts" at some point as the internal logic begins to fail and a GHz speed processor can ...


2

Usually when I've seen that, they share an 8bit data bus. I agree that for a 16bit data bus, it would not be used, both UB and LB should be low. This chip puts the upper byte on different pins from the lower byte and alternately sets the other 8 bits to Hi-Z, so they can still be tied together (0,8) (1,9) etc.


2

In general, if things keep on not working, open the documentation and follow the synthesis style guide which will show you the exact VHDL/verilog you need to write to infer your favorite blockRAM. That said, you should be able to write a simple behavioral model for easy cases such as this, as long as you follow the datasheet for the iCE40 family, which says ...


1

Your terminology is very wrong You do not "input memory to a buffer" You do not "request that data by giving it the "buffer"" This makes me fear that you are very much out of your depth here. You read or write a memory. Static memories, as you have here, are the simplest to read and write. For that you have to connect the computers address and data bus ...


1

DQS is aligned with the data bus DQ, not the clock. It is used to precisely time where the DQ data are to be sampled. It’s a necessary complexity in order to support the clock speeds contemporary DDRx DRAM can achieve, in a way that supports a large number of chips and groups-of-chips (that is, ranks.) DQS and DQ do have a rough alignment with the input ...


1

This isn't about refresh. The bus may be running at a higher speed than a single RAM module allows. Then you either need wait states on the bus or interleaved RAM modules, so subsequent accesses —the most common— touch the first module, then the second module, the first again etc. The bus throughput almost doubles, given subsequent reads or writes are ...


1

Those are manufacturer's codes for items you can purchase. 1) Difference is you get one box with two 8GB sticks or one box with one 8GB stick. Sticks are all identical. Sometimes buying a pack of 2 is cheaper than two packs of one. 2) You might want to ask the manufacturer about this, as it does not have anything to do with electrical engineering.


1

You appear to be describing a FIFO chip, and contrary to the other answers, they do exist as COTS products. For example, IDT has a line of chips of that type. Unfortunately, the 1 MB parts (512k × 18 bits) have prices on the order of $200 in small quantities. But the rest of your functional description is so vague that I can't be sure. Also, if ...


1

Since @rdtsc has provided an excellent answer let me share an experience which might be what you are thinking: In a remote part of Canada a building used a heating/cooling system from a very reputed company. But grid power was unreliable. If power was lost it took over 2 hours for the system to reboot (power interruptions happen more than once per day in ...


1

The binary image only provides the contents of the Flash ROM memory; it does not provide an "image" of the RAM. Once programmed, the microcontroller does the same thing every time you turn it on...that wouldn't be possible if we tried to download data to the RAM as part of the programming process, because the RAM data is not saved when we cycle power. Now, ...


1

Some DRAM can be affected in that way, because storing a charge on a capacitor is a linear operation, and the effects of perturbations accumulate. But the ferroelectric material used in FRAM is bistable, and requires a certain minimum energy to change state. If any individual perturbation isn't enough to change the state, then the effects of multiple ...


1

These address pins are used in a multiplexed fashion for row and column addresses. Extremely simplified, it means that accessing 4 GB (which needs 32 address bits) only 16 address bits are sent at a time in two parts. In reality it is slightly more complicated as there are X rows and Y columns and Z banks in a single chip and there are multiple chips per ...


1

SRAM - A 6 transistor structure holds a 1 bit of information. No need to worry about the device losing the information over time (whilst powered). Needs more circuits to store information than a DRAM. DRAM - A single FET and capacitor structure is used to store 1 bit of information. Capacitor loses charge slowly due to leakage. A refresh circuit is hence ...


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Flash: NOR and NAND Both NOR and NAND flash use a floating gate to store data. The difference between them is a trade-off of density and speed vs. reliability. Floating Gate Structure: From here: https://searchstorage.techtarget.com/definition/floating-gate A more detailed description of Flash here: https://www.embedded.com/design/prototyping-and-...


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when I plug a linux stick into my computer my computer is unable to execute from that stick in the same way that an avr is unable to execute from external storage. (there are exceptions but not in the arduio case) How it works in your computer is code that is on rom (can execute from there) runs and loads code into ram which knows how to load code from ...


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