New answers tagged ram
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For DDR4 and DDR5, is tCCD_l timing to be obeyed for accesses in a single row as well?
Same bank, different row is actually one of the worst case scenarios for timing.
Remember that there is only one set of buffers in a bank that can do the actual reading/writing to the DRAM cells.
You ...
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What is the theoretical maximum capacity of 72-pin RAM modules?
Although you could build a CAS/RAS decoder, that would introduce latency: you'd need the encoded CAS/RAS information before deciding which set of chips to address, and which physical CAS/RAS signal to ...
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Accepted
What is the theoretical maximum capacity of 72-pin RAM modules?
Did you look at the functional block diagrams in that datasheet?
The four CAS# lines are used to enable the four bytes of a 32-bit word.1
Furthermore, two RAS# lines are used for each 32-bit word. ...
- 171k
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DS1220 vs X2816A
The Xicor chip is an EEPROM, not a RAM. It has a write cycle time of 10 milliseconds, which means it isn't just a drop-in replacement for battery-backed SRAM, which is what the Dallas chip is. The ...
- 171k
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