39

I still don’t understand what a register physically is... Where on a processor is it? What do they look like? How big are they? Physically it is made from the same structures that make up all the other logic in the processor. Depending on the implementation that could be transistors created on a silicon wafer, or discrete transistors, or vacuum tubes, ...


33

In the end, all programs are machine code, regardless of whether the source language was assembler or a high-level language. The important thing is that there are hardware mechanisms that limit what a given process can do, including "messing with" registers that could affect other programs or the operating system itself. This started with a simple ...


30

You've got most of it down. Let's start here: there are billions of transistors inside a computer's processor. Many of those transistors are used to create registers. Here's a basic description of the building-blocks of a register, from smallest to largest: Transistor: There are many different types of transistors. For the sake of simplicity, the following ...


23

the half of the byte in memory is the opcode and other half is the address Well, that's one way of doing it, but there are lots of ways of doing it. Instructions don't have to contain the address. Instructions containing the address or operand is usually known as "immediate" mode, but there are various other addressing modes. You could have those ...


20

The word banking is used in two different senses when applied to registers. Banked Registers for Interrupt Handling The sense with which the StackOverflow question is concerned is similar to the use in (memory) bank switching (used by some 8-bit and 16-bit processors) in function. The names of a collection of registers are mapped to a different collection ...


15

Two factors work against your idea: the optimal chip production processes for (D)RAM and logic (CPU) are different. Combining both on the same chip leads to compromises, and the result is far less optimal than what can be achieved with separate chips, each built with their own optimal process. fast memory (registers) takes more die area and consumes more ...


14

Rom(=Read only memory) is a brute force (=absolutely non-minimized) way to implement a combinatoric circuit. Current state bits and inputs together are address, the data stored into that address contains the next state and possible output bits which both can depend on current state and input bits. When one builds a state machine using standard parts, he ...


13

I'm guessing you've encountered this in terms of PIC programming. PICs originally had I/O ports handled in a very direct manner - you could read what values they had externally, or write what values you output, both on the same address. The downside of this was that the value you were trying to output might not match the state on the pin - something else ...


11

You're forgetting a couple of important facts: A flip-flop isn't a single atomic gate, but made up of multiple gates. It takes time for a signal to pass through a gate (or propagate). There is no such thing as a pure square wave. Take this diagram of a transparent latch: Assume each gate requires one "time unit" to propagate the signal. The D ...


11

Those denote the bits within the register. The bits are number 7, 6, 5, 4, 3, 2, 1, 0 so register 0xF4 is build up: Control register 0xF4 bits: 7 6 5 4 3 2 1 0 <---> osrs_t bits In <----> you can set the temperature measurement and oversampling setting (osrs_t). In Table 5 ...


10

Flip-flops are single bit devices with two stable states. The outputs are typically Q and \$\mathsf{\small \overline{\text{Q}}} \$. There are several kinds, here are probably the most common: SR flops have two inputs, S (Set) and R (Reset). As they name implies, asserting either of these either sets or resets the flip-flop. After the input is de-...


10

Many multitasking operating systems use a data structure called a Process Control Block (PCB) to take care of the register overwrite problem. When you run your code, the OS creates a new process to keep track of it. The PCB contains information about your process and space allocated to hold register contents. Let's say process A is currently running on the ...


9

First of all I think you missed a | symbol: TCCR1A = ((1 << COM1A1) | (1 << COM1A0) (1 << CS11) | (1 << WGM13) ); TCCR1A = ((1 << COM1A1) | (1 << COM1A0) | (1 << CS11) | (1 << WGM13) ); Second: Bits COM1A1 and COM1A0 are in register TCCR1A Bits CS11 and WGM13 are in TCCR1B TCCR1A and TCCR1B are ...


9

Can anyone explain to me what a strange protection if the password(code) 5Ah is known? It protects you from random modification by runaway code, e.g. on stack overflow. Why RCKEY always read as 69h(not 5Ah)? So you cannot simply read->write it - part of the protection mentioned above. Microcontroller code often contains code that read-modify-writes a ...


8

No, because then you could possibly clear other bits you didn't intend to by accident. It's a little hard to verbalize, but it is very easy to write a 0 simply by, well, writing a 0. You must deliberately choose to write a 1. Since every position expects a 1 in order to clear it, write a 1 only to bit 5: STATUS = _BV(TX_DS);


8

There is insufficient room on the CPU die to fit such a vast amount of memory, current RAM memory relies on DIMMs with multiple chips. The cost is also an issue, CPU die space is more expensive because of a different manufacturing process. We currently have CPU caches (memory on the die) for this purpose and they are as big as possible. For most purposes ...


8

If you just write a function that reads the ADC result into a variable, does some math on it, and then writes the result to PWM, and if you use a decent compiler with optimization turned up, then the critical data will probably end up in a register whether you want it to or not. That's really not that much different from setting up DMA just so that you can ...


7

Yes, this is exactly the right place to ask your question. Yes, R-2R topography is the simplest to design (and I think best) way to make a homebrew DAC (wkthout using PWM). As for challenging yourself, it sounds to me like you may be about as masochistic as I am (kudos for having the guts!). This is a really involved project for a beginner. Your R-2R ...


7

Each digital circuit can only work with a given amount of capacitance load which is given by the logical effort and its fan-out. If you connect too many blocks (latches in your case) at the output of the same rising edge detector, it would not work properly and would lead to lot of setup or hold violations after synthesis. The reason is you need to drive too ...


7

The ‘bitness’ of a cpu is a disputed topic. My take is the width of the ALU and data path. The fact that the Z80 is believed to be an 8bit cpu but had only a 4 bit ALU contradicts this. Your chip has an ARM Cortex M4 cpu. ARM declares this as a 32bit cpu - who am I to argue? Its alu can do a 32bit add in one clock, but not four 8bit adds or two 16bit adds.—...


6

From my textbook, Digital Design and Computer Architecture, Harris and Harris, pg. 88 An important note When you are attempting to find the propagation delay of a combinational circuit with multiple elements, you must add the propagation delay through the critical path. However when you are attempting to find the contamination delay of a combinational ...


6

The BSRR has bitfields that allow you to set and clear bits in a port atomically--without a read-modify-write operation. Instead of reading the ODR value, ORing it with the bits to set, and writing it back, you simply perform a single 32-bit write to the BSRR to set or only the relevant bits. This often means you don't have to disable interrupts or use ...


6

Instead of AND gates you need to use tristate drivers. These drivers go to a high-impedance state when they are not enabled, which allows some other device on the bus to control the bus signal voltages. Presumably, the control logic allows only one register output to be enabled at any given time. Logisim calls these drivers a "controlled buffer", by the way....


6

No. The CPU registers and I/O registers are in their own set of locations independent of the on-board SRAM. They can be accessed via normal memory access instructions, but they do not take away from the size of available SRAM. For illustration, here is the data memory map of the ATmega128A, a AVR device with a full complement of CPU registers, 224 I/O ...


6

There is DRAM which uses a capacitor to store a charge to represent the stored bit. A row of transistors is used to connect a row of capacitors to the read/write circuitry to put the data into a set of latches to read it and also feed it back into the row to refresh the capacitors' charge which was depleted into the latch's input. The capacitors will self ...


6

The way to choose how to declare your signal is not by how it will be physically instantiated, but by how you will syntactically assign its value. If the signal is driven by assignments in a procedural block (a block beginning with always or initial), then it must be declared as reg. If the signal is driven by continuous assignment (an assign statement) or ...


6

These instruction sequences are not equivalent, they are 4 different ways of implementing stacks. A is a top-down stack where the stack pointer addresses the most recent value. B is a top-down stack where the stack pointer addresses the next insertion point C is a bottom-up stack where the stack pointer addresses the most recent value D is a bottom-up stack ...


6

This look like a general representation of sequential logic. It could be Read Only Memory: Any boolean function or logic gates combination can be implemented as a look-up table, and look-up tables are equivalent to pages of read-only memory where the inputs are the address and the outputs are the content of the memory.


6

My question is, since i have to put the conversion result into CPU to be processed anyhow, cant i just store it directly in processor registers without involving DMA or SRAM at all and process is right away? No, this is not possible in an Cortex-M4. Moreover, you would not want this to be possible. To make it clear why: If you write your program in "...


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