38

I still don’t understand what a register physically is... Where on a processor is it? What do they look like? How big are they? Physically it is made from the same structures that make up all the other logic in the processor. Depending on the implementation that could be transistors created on a silicon wafer, or discrete transistors, or vacuum tubes, ...


33

In the end, all programs are machine code, regardless of whether the source language was assembler or a high-level language. The important thing is that there are hardware mechanisms that limit what a given process can do, including "messing with" registers that could affect other programs or the operating system itself. This started with a simple ...


30

You've got most of it down. Let's start here: there are billions of transistors inside a computer's processor. Many of those transistors are used to create registers. Here's a basic description of the building-blocks of a register, from smallest to largest: Transistor: There are many different types of transistors. For the sake of simplicity, the following ...


18

The word banking is used in two different senses when applied to registers. Banked Registers for Interrupt Handling The sense with which the StackOverflow question is concerned is similar to the use in (memory) bank switching (used by some 8-bit and 16-bit processors) in function. The names of a collection of registers are mapped to a different collection ...


15

Two factors work against your idea: the optimal chip production processes for (D)RAM and logic (CPU) are different. Combining both on the same chip leads to compromises, and the result is far less optimal than what can be achieved with separate chips, each built with their own optimal process. fast memory (registers) takes more die area and consumes more ...


14

Rom(=Read only memory) is a brute force (=absolutely non-minimized) way to implement a combinatoric circuit. Current state bits and inputs together are address, the data stored into that address contains the next state and possible output bits which both can depend on current state and input bits. When one builds a state machine using standard parts, he ...


11

I'm guessing you've encountered this in terms of PIC programming. PICs originally had I/O ports handled in a very direct manner - you could read what values they had externally, or write what values you output, both on the same address. The downside of this was that the value you were trying to output might not match the state on the pin - something else ...


11

Those denote the bits within the register. The bits are number 7, 6, 5, 4, 3, 2, 1, 0 so register 0xF4 is build up: Control register 0xF4 bits: 7 6 5 4 3 2 1 0 <---> osrs_t bits In <----> you can set the temperature measurement and oversampling setting (osrs_t). In Table 5 ...


10

Flip-flops are single bit devices with two stable states. The outputs are typically Q and \$\mathsf{\small \overline{\text{Q}}} \$. There are several kinds, here are probably the most common: SR flops have two inputs, S (Set) and R (Reset). As they name implies, asserting either of these either sets or resets the flip-flop. After the input is de-...


10

You're forgetting a couple of important facts: A flip-flop isn't a single atomic gate, but made up of multiple gates. It takes time for a signal to pass through a gate (or propagate). There is no such thing as a pure square wave. Take this diagram of a transparent latch: Assume each gate requires one "time unit" to propagate the signal. The D signal ...


10

Many multitasking operating systems use a data structure called a Process Control Block (PCB) to take care of the register overwrite problem. When you run your code, the OS creates a new process to keep track of it. The PCB contains information about your process and space allocated to hold register contents. Let's say process A is currently running on the ...


9

Register layout is generally determined by the hardware designer. There's usually a reason for unused bits - most likely first: Functionality from an earlier design was removed, the bit flags are now reserved to avoid confusing old revisions of software (backwards compatibility). To leave space to implement behaviour in future revisions. Or indeed the bits ...


9

Can anyone explain to me what a strange protection if the password(code) 5Ah is known? It protects you from random modification by runaway code, e.g. on stack overflow. Why RCKEY always read as 69h(not 5Ah)? So you cannot simply read->write it - part of the protection mentioned above. Microcontroller code often contains code that read-modify-writes a ...


8

The source of the confusion is that there are (in general) two kinds of things that can be called "registers". The first is probably what you are familiar with: in ARM, it's registers R0, R1, R2, ... R12, SP, LR, PC and in x86 it's eax, ebx, ecx, edx, ebp, and so on. These can also be called "core registers" or "processor registers". They don't have ...


8

No, because then you could possibly clear other bits you didn't intend to by accident. It's a little hard to verbalize, but it is very easy to write a 0 simply by, well, writing a 0. You must deliberately choose to write a 1. Since every position expects a 1 in order to clear it, write a 1 only to bit 5: STATUS = _BV(TX_DS);


8

A few obvious ones: They take up space in your instruction encoding. If you had 256 registers, for instance, you'd need to use 8 bits in an instruction just to specify a single register. This could increase the overall size of instructions, or limit the types of instructions that can be encoded; having fewer registers, generally speaking, makes your ...


8

There is insufficient room on the CPU die to fit such a vast amount of memory, current RAM memory relies on DIMMs with multiple chips. The cost is also an issue, CPU die space is more expensive because of a different manufacturing process. We currently have CPU caches (memory on the die) for this purpose and they are as big as possible. For most purposes ...


8

If you just write a function that reads the ADC result into a variable, does some math on it, and then writes the result to PWM, and if you use a decent compiler with optimization turned up, then the critical data will probably end up in a register whether you want it to or not. That's really not that much different from setting up DMA just so that you can ...


7

Yes, the entire line of Burroughs mainframe computers starting in 1961 with the B5000 used a stack architecture. In this architecture, managing the data flow to and from the stack is not actually too much of a bottleneck for performance. A bigger issue is the fact that a "zero address" machine needs a lot more instructions to complete a given task than a ...


7

Yes, this is exactly the right place to ask your question. Yes, R-2R topography is the simplest to design (and I think best) way to make a homebrew DAC (wkthout using PWM). As for challenging yourself, it sounds to me like you may be about as masochistic as I am (kudos for having the guts!). This is a really involved project for a beginner. Your R-2R ...


6

Turns out I missed a crucial detail in the accompanying text, and the registers are indeed composed out of two (master-slave) sub-registers: The Use of Master–Slave Registers Note that the contents of the PC are incremented within the same clock pulse. As a direct consequence, the PC must be implemented as a master–slave flip–flop; one that ...


6

registers I believe you're referring to this drawing: The register file is an array of 32 general purpose registers which resides in the AVR's CPU. The registers are tightly coupled with the ALU (Arithmetic and Logic Unit) so that operations on the register data can be performed much faster than data which has to be fetched from (external) RAM. A ...


6

The I/O ports of an AVR are set to INPUT / Tri-State / Hi-Z (DDRx = 0x00) upon reset. Most microcontrollers (if not all?) have this behavior. It's the safest state for a pin to be in. So yes, you can rely on the ports to be set automatically as inputs. Some excerpts an the ATmega16 show exactly that: The Port C pins are tri-stated when a reset condition ...


6

It depends on the particular processor whether "registers" are in the same address space as regular data memory or separate. In either case, if there are multiple of them each one still needs a address. Let's say the processor has 16 registers that are tightly coupled to the CPU and implemented separately from data memory. Those registers still have to be ...


6

You have the op code for ANDI wrong, it's 0111 KKKK dddd KKKK. Using the assembler, I get 0x7120 as the machine code for ANDI r18, $10, which is 0111 0001 0010 0000. 0010 for dddd is 2, which represents r18, because it's the third register from r16 to r31. Only the upper 16 registers are valid for the ADDI instruction. 0000 is r16, 0001 is r17, and 0010 is ...


6

No. The CPU registers and I/O registers are in their own set of locations independent of the on-board SRAM. They can be accessed via normal memory access instructions, but they do not take away from the size of available SRAM. For illustration, here is the data memory map of the ATmega128A, a AVR device with a full complement of CPU registers, 224 I/O ...


6

Instead of AND gates you need to use tristate drivers. These drivers go to a high-impedance state when they are not enabled, which allows some other device on the bus to control the bus signal voltages. Presumably, the control logic allows only one register output to be enabled at any given time. Logisim calls these drivers a "controlled buffer", by the way....


6

First of all I think you missed a | symbol: TCCR1A = ((1 << COM1A1) | (1 << COM1A0) (1 << CS11) | (1 << WGM13) ); TCCR1A = ((1 << COM1A1) | (1 << COM1A0) | (1 << CS11) | (1 << WGM13) ); Second: Bits COM1A1 and COM1A0 are in register TCCR1A Bits CS11 and WGM13 are in TCCR1B TCCR1A and TCCR1B are ...


6

The BSRR has bitfields that allow you to set and clear bits in a port atomically--without a read-modify-write operation. Instead of reading the ODR value, ORing it with the bits to set, and writing it back, you simply perform a single 32-bit write to the BSRR to set or only the relevant bits. This often means you don't have to disable interrupts or use ...


6

The way to choose how to declare your signal is not by how it will be physically instantiated, but by how you will syntactically assign its value. If the signal is driven by assignments in a procedural block (a block beginning with always or initial), then it must be declared as reg. If the signal is driven by continuous assignment (an assign statement) or ...


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