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52

On PIC and dsPIC chips, I have observed the following causes of unexpected reset. Hardware: Reset pin driven low or floating. Check the obvious stuff first! ESD coupling into the reset pin. I've seen this happen when completely unrelated equipment gets turned on on the same desk. Make sure there's enough capacitance on the reset pin, possibly as much as 1 ...


37

Unless you have an initial state programmed, it will be more or less random. Although this may vary with different SRAM implementations. You also say "blank". Some might think that random is "blanker" than all 0's. SRAM memory stores memory on back to back inverters. This forms a bi-stable system (two very stable states with metastability dividing ...


37

x86 instructions often take up more than one byte, and a reasonable reset routine will almost certainly point to multiple instructions. If the reset vector were to refer to 0xFFFF_FFFF, then only a single byte instruction would fit into that memory mapping; almost any useful reset functionality would thus require instructions that cross the 0xFFFF_FFFF/...


33

A watchdog timer can guard against hardware bugs in buggy piece of ... cutting edge microcontrollers. One that we recently used, from a famous brand, had I/O pins that occasionally missed their interrupts, sometimes did not start up correctly, and where the integrated watchdog sometimes failed to reset the system in a known-good state. This did not show up ...


32

It is hard to argue, that the internal clock of the internal watchdog is actually independent of all the other clocks and always running like it should. So for certification it is usually much easier to place an external watchdog on the board and say: look there is our watchdog, it must be triggered by the MCU at that interval, which is shorter than our ...


25

The reason why it is 16 bytes below the top of memory comes from how the original 8086 CPU registers were loaded during reset. And even that may have something to do with compatibility for older 8085 CPU. And this compatibility has been carried over to later chips, such as 80286, 80386, etc. Sure, they could have selected any value, but since interrupt ...


21

You should respect your voltage isolation. The way you have placed (and routed) resistors R16, R13 R10, R2, R31, and R4 compromises the isolation barrier created by your opto-isolators. Below I have marked your existing layout with your isolation path, which is fairly poor: Have a single isolation zone that is as wide as possible (the width of your opto-...


16

Yes, it's a good idea - the only downside is a bit of extra code size, and you have to decide what to do with the trap (emit a message on the serial port? turn on a "FAILED" light? Silently reboot? etc)


15

Atmel AVR042: AVR Hardware Design Considerations tell us that the capacitor on the reset pin is not necessary. Personally I think it's overkill. There is no reason for you to continue making dozens of AVR circuits, each and every one with that redundant capacitor. As for the reset pullup resistor: The reset line has an internal pull-up resistor, but if ...


14

In all likelihood it isn't really a "set/reset" signal, so much as a signal that can be configured to be either set or reset depending on how the device is configured. Note that in figure 3.2 (copied below for clarity), it says "flip-flop with optional [...] set or reset controls". Similarly it will also be the configuration bits that disable the signal ...


13

My informal rule is: If an interrupt is enabled, then you should have code that handles it. If you don't write code for an interrupt, disable it. If you can't disable it, write code for it. Even without that rule, though, the data sheet explicitly answers your question: If the user does not intend to take corrective action in the event of a trap ...


12

The watchdogs built in to microcontrollers have particular properties that mean they themselves can fail in ways that a different external watchdog might not. For example, a common design is to use a watchdog timer running from a low power RC oscillator. That oscillator can fail. An external watchdog based on capacitor discharge rather than an oscillator ...


11

You didn't show a schematic, but I don't see any obvious bypass caps or local on-board power supply reservoir caps. That and lack of good grounding is quite likely causing the problems. As others have said, you should also leave proper isolation distance between the AC and DC sections, and at least try to make somewhat of a ground plane. You have a large ...


11

Some products must meet safety requirements, either determined by the manufacturer or to meet international safety standards such as IEC 60730-1, or the older UL1998 which is still in use in the US. The internal watchdog functionality in any given microcontroller may or may not be adequate to be used. An external WDT may be used in combination with the ...


10

Note: Although Bimplerekkie's answer is good and reasonable, another explanation is possible, which was also hinted in a now deleted answer from DrFriedParts and accompanying comments by Ignacio Vasquez-Abrams. Since I found relevant documentation about this other explanation, I think it is better to give it here (the true reason why that diode was put in ...


10

The clock undoubtedly operates charge pumps within the chip that provide bias voltages for various functional areas. Without proper bias, leakage currents are probably higher than the transistors are really designed to handle long-term.


9

I had intended to only comment, but I found I had too much to say: Follow Spehro and Alexey's advice. There are multiple issues here. Perform all of the fixes, even if you find that just a snubber or decoupling capacitor seems to do the trick. The load is 220AC. Trying to control bell. Please note that when there is no load, the relay command fully ...


9

What I think you need to do is make sure that the charge from the ESD pulse does not reach the MCU. You have done all the right things to try and absorb this charge. However, the charge comes from a capacitor with a very low series resistance so you would need devices with a very low series resistance as well to be able to absorb the transient of the ESD ...


9

The way that you propose is not a good way to switch the power to the load. You should instead switch the VCC power side and keep all the GNDs common between the MCU and the power switched device. The technique used to achieve this would be to use a P-Channel MOSFET for the power switch and then an additional small signal transistor to provide level ...


9

You're using a "glitch" to reset your counters. In other words, when the reset pulse starts, it immediately removes the conditions for its own creation, so it's only as wide as the propagation delay through one of the counters. Clearly, one of those counters is faster than the other, so it resets successfully, while the other does not. This is why this is ...


8

The RESET-pin must be properly driven by a reset circuit monitoring over/under voltage and creating a long enough reset signal. With that in mind my experiences with an uncontrolled hardware reset comes then from: Crosstalk from switching lines into the RESET pin/line(make them short) Ground shifts/loop caused by switching on/off external high current load ...


8

The reset capacitor is there to block DC signals. The capacitor acts as a pulse transmitter so to speak, where the auto-reset line will be pulled low briefly by an external source, and the capacitor will act as an AC pull-down, for the effect of a single reset trigger on the microcontroller. If there was a reset button, and it was pressed down by a human (or ...


8

The assertion timing doesn't matter because the whole point is that all the elements of the circuit enter a valid/known reset state. It generally doesn't matter what order they do it in, only that the final state is predictable. De-assertion is a problem because if some flip-flops come out of reset before others, they may start changing state while others ...


7

Yes, always connect the Reset Pin of the ATtiny to VCC through a 10k resistor. It can't hurt, and it can help (prevent your device from resetting randomly).


7

I always just use a 10k pullup resistor to Vcc on the /Reset pin and have never had any problems. It's also generally a good idea to include a 100nF capacitor near the Vcc pin between Vcc and GND for stable chip operation. In my opinion the capacitor on the reset pin is not necessary, which is to say I have never included one in any AVR circuit I have ...


7

An asynchronous reset will always be performed regardless of the state of the clock; a synchronous reset on the other hand requires a clock pulse before it will take effect. Most reset inputs on counters are asynchronous, but confirm this with the datasheet before assuming anything.


7

Your layout is not very good (in particular the Vcc path is long, thin and inductive), and that is about the worst relay you could choose (it is about the cheapest, however). A better relay with high isolation (preferably with non-counterfeit European approvals), ground and Vcc polygon pours (you've got Altium, it's a very good and expensive program, you ...


7

The ATmega can work without a reset button. Powering down the controller will reset it, as the O.P. expected. In-circuit programmer will also reset the controller every time new firmware is loaded. If it becomes apparent that a reset button would be a nice thing to have, it can be wired like this: Source: Atmel application note AVR042 (AVR Hardware ...


7

Is power cycle reset different as compared to reset pin reset? Yes. There are some semiconductor behaviours where only loss of power will allow previous behaviour to resume. An SCR is a type of component where this behaviour (i.e. only loss of power allows previous state to resume) is normal, and SCR-like structures exist within most ICs. Is this an ...


6

With option B, you'll need a separate supply for the watchdog. Plus, interrupting power to the entire circuit is drastic step that will make other things (such as debugging) that much more difficult. It would be better to design the system so that the microcontroller has the ability to reset/restart all of the other functional blocks under firmware control, ...


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