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34

1) Equalisation of length of pairs of traces From Board Design Resource Center 2) Delay (e.g. of clock for timing purposes)? See also Adding delay intentionally 3) Reduce signal reflections due to discontinuities in trace width? from Circuit Board Layout Techniques See also How should I lay out timing matched traces?


30

I can think of three options: Zoom out as much as you can then use the route tool on the tiny board, this catches the air wire, then zoom in again and route it. You can also disable the top and bottom layers so the air wire becomes more visible. Yet another option is to run the provided "length.ulp" script (File->Run... or ULP button). This script shows a ...


29

The industry term for this is via in pad. It's not a problem when you hand-solder components. It can cause problems during automated SMT assembly. Solder, which was applied to the pad as a solder paste, can drain through the via and there will be an insufficient amount of solder to hold the part. (Image came from this blog entry, which illustrates the ...


26

One very good reason, as I learned myself from a recent prototype, is reversing the physical layout of the IC in a circuit. I plugged a through-hole version of this microcontroller into a socket backwards, and spent about an hour with an oscilloscope trying to determine why pins were not behaving as expected. When I discovered the IC was in backwards (and ...


26

At I2C speeds, vias will cause you absolutely no problems at all. At least, no problems in terms of track resistance, capacitance or inductance. However, if you have a 2 layer board, then using both layers is best done systematically, otherwise you can lead yourself into problems. What many people do is to dedicate one layer of a board to ground. This ...


25

Manhattan routing is a PCB routing strategy. You use one dedicated layer for horizontal tracks and another layer for vertical tracks. No horizontal tracks are allowed on the vertical layer, and no vertical traces are used on the horizontal layer. This means that most connections will go trough a via, but this strategy can provide surprisingly dense boards ...


24

The split ring is preferable. A ring that goes all the way round acts like a loop antenna or may act as one closed winding of a transformer. The loop antenna may radiate or pick up electro-magnetic interference and if it acts as a primary transformer winding, the circuitry around the microcontroller in the middle may act as the secondary winding and become ...


23

As an addition to Armandas' answer: If you want to use vias, there is a simple trick to swap the lines: Rotate the vias by 90 degrees, i.e. put them "above" each other. If you enter both vias from the left in the top layer and leave them to the left in the bottom layer, both lines are swapped at no expense: (Just a quick drawing as my schematics computer ...


14

I don't think there exists such a strong preference for 45 degree angle. I have seen an old Tektronix Oscilloscope (Tek 2213 to be precise) board with traces that looks like hand drawn :-)


14

Yes, most likely that's fine. You have to make sure each chip is set up to expect a ready clock in, not to drive the crystal itself. You have to look at the datasheets, of course, but most likely the devices can be set up that way. However, there may be a less expensive way. Very likely at least one (probably both) of the chips can drive a crystal ...


14

There is an ULP called zoom-unrouted. When you run it, it will automatically zoom your view to the first airwire it finds. Very useful. Here is the link: https://cadsoft.io/resources/ulps/349/


14

Look at a map of Manhattan: streets are straight and at right angles. That's what you do on your PCB: horizontal and vertical lines. There's also the concept of "Manhattan distance". That's the distance measured vertically, then horizontally, instead of a direct line.


14

why are they all not connected to each other on the top layer, since they are all the same net ? Because this is a switching converter. In switching converters very high currents can flow, often these or only very short current pulses. If we "just" connect everything to the ground plane directly it is unclear where these currents actually flow. Yes all is ...


13

There isn't one. That said, there are some thing I've gathered over time. What you do with the ground planes depends heavily on what you're trying to do. You could be trying to provide low impedance paths, or you could be trying to isolate one area from another, or you could be trying to deal with EMI. There certainly is a performance penalty for doing ...


13

There's nothing wrong with via in pad per say. As other people have noted an open via in pad can lead to soldering issues as the solder is sucked down the via hole. Hand soldering you'll be fine of course, also for small runs the manufacturer can just pre-fill the hole with solder by hand with an iron or a hot air pen. This usually eliminates most of the ...


12

In this case it seems wholly acceptable to interchange data bits and to interchange address bits. This is not universally the case, as you allude to in your question. In this case the device is a static RAM - a quick flick through the AS6C1008 datasheet did not indicate any ability to do fast acceses of any sort or any address related timing dependancies. ...


12

If I were to suggest how to route this I would propose something more like this:


12

Your interpretation is overly simplistic. Real FPGAs have a complex hierarchy of routing resources, some for local connections only, some for medium-range connections and some for spanning the entire chip. These structures have been developed over many years of studying application designs, trying to strike a balance between the area required for routing ...


11

The 90º intersection will not be a issue for most traces. If your trace is very thin (< 15 mill) and/or the PCB boards aren't being professionally manufactured you can use mitered traces (chamfer) as helloworld922 pointed out. Adding chamfers will eliminate the 90º intersection and help to strengthen the trace. For high frequency traces (> 1GHz) it also ...


11

According to the help system of eagle, you can use the command RIPUP @; to ripup all polygons. You can limit this to polygons of a list of signals by RIPUP @ GND VCC MYSIGNAL; You can define a keyboard shortcut for RIPUP @; and another for RATSNEST; to simply toggle between filled and non-filled polygons. By the way: You can also en-/disable the filling ...


10

This may be a solution: It improves on your second option in that it keeps the connections to the power connector as short as possible, given the placement of the signal connectors. Your first option may not be too bad, however. You'll probably have a similar current flow as here: power and return path at the top and a pair at the bottom. You would only ...


10

Old timers might grumble about "etchant traps" ... acute angles can hold acid (well, FeCl) long enough to eat through the track - or not, depending on who makes the PCB for you. Consult with them if you are worried. But I was downvoted for pointing that out in a previous answer, so at least somebody thinks that's no longer a problem. As far as the signal ...


10

The primary advantage of a Manhattan route is that it can always be completed. You just need to have enough board area to accommodate all of the traces — but otherwise, you'll never find yourself unable to complete a route. This can be important if you need to get a layout done on a fixed schedule — the amount of work is roughly proportional to ...


9

In general, a device that connects N inputs to N outputs simultaneously is called a crossbar switch. As long as all the signals are digital unidirectional signals, such as the signals on a few SPI buses, a FPGA can be configured to dynamically route any of N inputs to any of N outputs. If N is small enough, you might also be able to do this with some other ...


9

You might try searching for solderable bus bars. They come in various sizes and shapes. You can solder them down to the PCB, and they provide masses of current carrying capability.


9

For a 2-layer board its pretty common to have one dedicated GND layer and use the other layer for all signals and power. In any case, prevent long traces on the GND layer, otherwise you may have unnecessary long GND return paths (due to the split GND plane/islands). For multi-layer designs, its good practice to have at least one 100% dedicated GND layer ...


9

This is not intended to be a complete answer rather it's a useful hint at what designers do when complex clock distribution is required. (courtesy of TI source) showing bad and good clock layout design : -


9

Regarding the signal it doesn't matter. The sharp angle might cause an acid trap, but with the trace width you are using should not be a problem. I would have routed horizontaly from the SMD pad to the vertical trace making a right angle.


9

For a simple two-sided board, start by creating a ground polygon on the whole bottom layer. The trick then is to get Eagle to route most of the connections on the top layer. To do this, make the cost of routing within a polygon high and the via cost low. Actually you want to start with parameters more likely to find a solution, then tighten up the ...


9

If the width/thickness of the track can carry the current AND The clearance between track and pad can withstand the voltage difference AND Neither track or pads are sensitive analogue nodes THEN It's probably OK


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