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26

At I2C speeds, vias will cause you absolutely no problems at all. At least, no problems in terms of track resistance, capacitance or inductance. However, if you have a 2 layer board, then using both layers is best done systematically, otherwise you can lead yourself into problems. What many people do is to dedicate one layer of a board to ground. This ...


10

The primary advantage of a Manhattan route is that it can always be completed. You just need to have enough board area to accommodate all of the traces — but otherwise, you'll never find yourself unable to complete a route. This can be important if you need to get a layout done on a fixed schedule — the amount of work is roughly proportional to ...


9

In general - yes. 100 kHz signal is very forgiving. Make sure to route both SDA and SCL in a similar fashion, close together. Also keep in mind the I2C total capacitance limit of 400 pF (you could run into that issue if the traces were really long).


8

Shouldn't be a problem. We are using vias on I²C which are running up to 800 kHz without any issues. The worst I have seen was a bad via, which created a series resistance in the I²C line. That affected the slew rate of the board so bad that the I²C communication failed. But that was on a prototype board and has never happened on a production board so far.


6

100kHz is pretty easy to move around. Our equipment has I2C EEPROMs mounted in a customer-replaceable part of the system, so that changes to calibration when that part is replaced will automatically be read by the controller. The cables for this can be metres long, and so far that's working OK. Admittedly we do have low-capacitance cables, but still, a ...


5

Just a few comments.... Lots of vias into the GND plane is not a problem. Number of vias drilled into a board does not have a huge impact on production cost. If it does find a different board fab shop. You need to make your stackup symmetrical in terms of copper density (as mentioned already in comments) to avoid board warp. It is not a good idea generally ...


5

It is all about the name of the nets (the interconnections between the parts) As you draw it, it is very clear that there are two distinct voltage sources with their positive terminal not being connected together. But from the logic of most circuit design programs, each piece of interconnection line has a name, and all lines with the same name are ...


4

As you have said PCB designing is not your strong point, so let's give you some pointers: Here are some general guidelines of PCB design in no specific order: Know your mechanical constraints. These can be anything from board dimensions, connector position, height limitations, and mounting holes, yes, don't forget those, if unsure, always add 3mm holes 5mm ...


3

I do ground on both layers, and use vias named Gnd to connect the top & bottom areas. 15, 20 mil clearane around pads where you will be hand soldering, makes life a little easier. 10 mil wide traces, clearance down to 10 or 8 mil if things are tight. Wider for power, current dependent. I don't see anything extreme there, 24 mil is likely plenty. No ...


3

You can pour Vdd on the top layer. The added capacitance will help decoupling. It's also slightly better usually to have Vdd on the top and GND on the bottom in case the bottom accidentally contacts something grounded. If you're doing pours it's a good idea to increase the clearance for the pours to something big like 0.02" (0.5mm) so as to improve ...


3

I'm by no means an expert in this area so I'm not sure if this will help or not, but I happened across a message thread on an Autodesk forum titled "USB Type C super-speed routing doubts" that seems related to your question. The designer seems to be using the same MOLEX(?) connector as shown in your figure. Perhaps it has information that'll help? https://...


3

A reference plane is not a requirement but most designs use one. Normally some of the return current will flow on the reference plane depending on how closely the differential pair is spaced. The reference plane also plays a role in the impedance of the differential pair. Achieving 100 ohms differential impedance on a PCB might be difficult without one. ...


3

As long as the RJ45 connector line pinout adheres to the standard, you shouldn't have any problems. The magnetics are a passive device, they don't care about RX + or RX-. You can even get away with RX/TX crossing on the connector side, as most modern NICs and switches have auto MDI/MDI-X capability. Some PHYs allow you to set the transmission polarity in ...


3

This is normal. It will connect components to 'nets'. Most software will show connecting nets. Because P1, P1, C1 and C2 are all on the 3.3V net, they will all be connected to each other, hence if you put the components anywhere near any component that is also connected to the same net, it will produce a connection line showing those components are ...


2

The points that you have highlighted are all valid, but don't really apply to your design, as a 8MHz microcontroller is not really considered high speed. In terms of EMI, what you should look at is rise time, rather than clock frequency, as the 8MHz frequency itself doesn't really cause issues, but a 1Hz signal with a fast rise time, can cause havoc. To ...


2

I would like to suggest that your proposal to use these blind and buried vias makes for a much more expensive board. You really should look at using more than 4 layers to be able to achieve your layout whether that be 6 or 8 layers. In all likelihood the cost for such board will be cheaper than your 4 layer board with the fancy expensive vias. More layers ...


2

Sounds right to me for the most part. If there is a very strong aggressor causing voltage fluctuation between the two reference planes, it could be an issue depending on the frequency relation to your signal. It depends on what level of spurious performance you need. I would honestly not worry about it much myself. The impedance calculation of a ...


2

it is recommended not to use power plane as reference plane if possible. To add to bitsmack explanation of the challenge of reference plane switching, I'd like to add an illustration on why the plane stitching is important. Take a look at the nice animation of electron "movement" in a transmission line: The image source is from Wikipedia. Note that the ...


2

If you have a power plane on the third layer, this becomes the reference plane for the bottom layer. This isn't a large problem: you just need to place a stitching capacitor near each trace where it transitions from top to bottom. These capacitors will only be connected to vias; one to the Vcc plane and one to the ground plane. (This is shown in the doc you ...


2

With the trace offset, there's an acute angle left between the pad and trace. There's been a lot of discussion over the years about the effect of 'acid traps' on the over-etching of the copper, and difficulty of washing out of the corner after etching. It doesn't seem to be such an issue with photoactivated etching systems, so may be a carryover that's no ...


2

You can't use Place -> Line (Shortcut P L) for routing. You're looking for Route -> Interactive Routing (Shortcut U T)


2

Your tracing options won't make things any better if the board has high dielectric loss. First you need to remove all the nonsense like shown below: This serpentine doesn't do any good. Make the traces as straight as possible, no wiggles. 10ps delay due to length difference won't make any noticeable change in the signal. If anything, do the length ...


2

I see a couple of serious problems here. The footprints you're using for diodes and resistors don't look right, unless you plan on mounting all of these components vertically. (And even that might be a tight fit.) Use horizontal footprints for these parts. The footprints you're using for connectors look like large terminal blocks, designed for high current ...


2

I just put the footprint into Altium to get a better sense of the size. I am able to fit a via with an 8 mil drill (0.203mm) and a 12 mil pad (0.305mm) between the rows of pads. These are not unusual sizes for vias either, and will not cost you extra (unless you're looking for 10 mil clearance (0.254mm). Using this size via provides more than 5 mil of ...


2

P1 and P2 are both power pins connected to 3.3 V and it doesn't matter whether you connect C1 to P1 or P2. In complex schematics, its common to place all decoupling capacitors at one end as shown: You can see a bunch of decoupling caps in the bottom right corner. While PCB layout, it's the designer's duty to make sure all pins get their decoupling cap. ...


2

Your problem is not that reversal is invalid, but that a USB C female to female coupler is invalid. All but the most basic USB C cables (3A USB 2.0) rely on an electronic marker inside the cable to detect the capabilities and orientation of the cable. Coupling two cables together is not a supported configuration. If it's for your own use only and you only ...


2

I'm assuming you are using the LQFP32 package and a 2-layer stackup, is that correct? What do you mean by "polygon" on bottom layer? Are you referring to ground pour? Is you part placement final? (I'm taking the liberty to assume "no"). Using screenshots of your layout, here what I would suggest: flip LDO circuit to top layer (there is still a lot of ...


2

The classic layout technique with double-sided boards that mostly contain DIP packages is to run traces (primarily) vertically on one side and primarily horizontally on the other. Power is routed first to keep the traces low inductance, and bypass capacitors are placed at every chip, usually. Typically the power pins are at the corners. That technique is ...


2

Wirewrapping - this box was all wirewrapped for connections. LEDs were soldered in place, didn't make sense for sockets for those. And then I wirewrapped right to the LED legs, which are square pins. 8 conductor cables (Dupont-style crimp housing headers with female-female wires) were made up to connect from the back of the card in the middle (what looks ...


2

Tyler mentioned this - don't know why he didn't frame it as an answer. But it's basically multiple layers on the board, at least for commercial applications (not hobbyist). Pretty much everything we do now is 14 layers minimum, up to 40 layers or more. Yeah, they're thick! At least 2 return planes, 6 or 8 routing layers, and no circuitry on the top & ...


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