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HDL is the catch all name for all hardware definition languages (Verilog, VHDL, etc.) in the same way Object Oriented can refer to C++, Java, etc. RTL on the other hand is a way of describing a circuit. You write your RTL level code in an HDL language which then gets translated (by synthesis tools) to gate level description in the same HDL language or ...

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HDL (Hardware description Language) is the type of language used, Verilog/VHDL versus a non-HDL javascript. RTL (Register-transfer level) is a level of abstraction that you are writing in. The three levels I refer to are Behavioural, RTL, Gate-level. Behavioral has the highest layer of abstraction which describes the overall behavior and is often not ...

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Every transistor has a current gain, usually $\beta$ or $h_{fe}$ in the datasheet. Typical values are on the order of 100. When the transistor is not saturated, then the base current and collector current are related by this factor: $$I_c = h_{fe} I_b$$ When the base current increases to the point where collector current can increase no more, the ...

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Can anyone tell me the difference between If-Else construct and Case statement constructs of a process in VHDL in terms of how the code is inferenced into RTL circuit by the synthesis tool ? The if-elsif-else construct infers a priority routing network: simulate this circuit – Schematic created using CircuitLab This corresponds to if bool_expr_1 ...

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From a discrete logic & HDL perspective: -Mealy machines (generally) have less states. Mealy machines change their output based on their current input and present state, rather than just the present state. However, less states doesn't always mean simpler to implement. -Moore machines may be safer to use, because they change states on the clock edge (...

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I would distinguish three possibilities: A VHDL variable has no hardware representation at all. Assume the following example signal a,b,c : integer; ... process ( clk ) is variable var : integer := 0; begin if ( rising_edge(clk) ) then var := a + b; c <= var; end if; end process; The variable var is not really synthesized as ...

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Here is a D flip-flop spec'ed to operate at 40 Gbps. Setup and hold times are advertised as 4 ps. It consumes only about 750 mW. These are manufactured with a SiGe process, although I don't know which one. There are several foundries offering SiGe process, including GlobalFoundries, TSMC, and TowerJazz.

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This is definitely possible. It is called an all digital PLL. Instead of a VCO, you use a numerically controlled oscillator, or NCO. An NCO is basically just a counter, called a phase accumulator, that you add some value to on each clock cycle, called the phase step. You then use one or more of the MSBs as the output. You could use the MSB to get a square ...

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If your synthesis tools are any good then you should use the * operator, set reasonable constraints, and let the tools do the heavy lifting. This is particularly true for FPGAs, which may very fast and dense multiplier cells. The Xilinx Spartan-3 series, for example, has some very nice 9x9 multiplier cells. If you insist on writing logic equations for your ...

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Jay covered almost everything to answer your question. One 'advantage' of the Moore machine is that it can be implemented in a Look up Table or SRAM memory. If your implementation is on an FPGA, let's say.. this might sometimes make the decision easy for you.

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If you use the value in a variable before you store it, you get the value that was stored last time the process stored it (in a clocked process, the value from a previous clock cycle). That is synthesised as a register or FF. Of course, in the first clock cycle you get garbage, unless you initialised the variable in a reset clause.

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In this old blog post, the author wrote and synthesized two functionally equivalent versions of VHDL code. One using if-else, the other using case. The result: I synthesized this code and got the exact results.Even the RTL schematic was exactly same for both of the programs. And his conclusion: This shows that 'case' and 'if...elsif...else' ...

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One example of such a bus is the AXI bus, which originated with the ARM processor, but is increasingly being used as a standard interface for FPGA IP in general. The two handshake signals are called TREADY and TVALID, and transfers only occur when both signals are asserted. I don't know if there is a "standard" name for this protocol. On occasion, I have ...

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Exactly how you implement it depends on the performance you need, which determines how deeply you pipeline it. I am going to assume that (do something) and (do something else) take approximately as long as the comparison x>=x_ref, and that the system is clocked slow enough that there is enough additional time to propagate signals through a multiplexer ...

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In a combinatorial block (always @* begin ...), you can't have an assignment statement in which the same signal appears on both the left and right sides. For example, you have several instances of: if (/* some condition */) begin shift_reg_next = shift_reg_next + 20'b0000_0000_0011_00000000; end That's a combinatorial loop. If the condition is true, it ...

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You need to go back to basics. Verilog is a hardware description language, not a programming language. Your code is describing hardware. Let's see what your code is trying to infer: module top( input a, b, x, output c ); Ok, we have a module. That's all fine. Now what does it do? always @(a or b or x) begin if(x) xor21 x1 (.a(a), .b(b), .c(...

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Setup and hold timing checks only make sense with post-layout information. A century ago, you could do timing analysis without layout structural information because the the device delays were overwhelming compared to routing delays. You can no longer do accurate timing analysis with RTL code. Some models are written to be used in both RTL and structural ...

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For part (2) - if the sensitivity list of a process contains other signals, and there is activity on those signals while clk = '1' then the process will operate multiple times per clock cycle. If it's a counter, that would be bad... Worse, synthesis would ignore the extra events (because there is no hardware feature to implement them) so simulation and ...

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Between floats (difficult to implement, resource-hungry) and integers (not enough precision), there's an intermediate: it's called fixed point math. Fixed point isn't much more difficult than integers to work with. And it is sufficient in your case. The basic idea is that you represent each value by an integer number. The correspondance between both is done ...

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First of all, Verilog is a Hardware Description Language used to describe a collection of digital hardware, and a module is just a way of hierarchically encapsulating your description. Each module boundary can be physical, like the pins of an FPGA or IC, or printed circuit board, or it can be logical, like a data path or controller. In any case, a Verilog ...

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Latch clock A on the rising edge of clock B. If the result is high then A arrived first. Of course this is assuming you have zero setup and hold times on the data inputs of your latches or that you know the phase shift is always going to be of a certain magnitude. In the real world with small phase shifts it gets a lot harder to be sure.

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It's a typo. In the GameOver state, you have load_dcard3 = 0 twice and don't assign to load_pcard3.

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Soft cores are standard logic modules, written in Verilog or VHDL. They are called 'soft' because they are implemented in the re-programmable logic of the FPGA. You can edit and modify a soft module to tailor it to your needs. If you decide to change the module later, you can just re-program it, and the gates will be re-arranged according to your changes. ...

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If I recall correctly, you can use the set_dont_use command to tell Design Compiler not to use certain library cells.

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If the issue is power distribution at your chosen supply voltage (say,5V) there are a few typical answers: 1) Thick wires, busbars as Connor says, to minimise voltage drop 2) Distribute a higher voltage, then each card has its own 5V regulator to maintain the correct voltage locally 3) Design and test each block for correct operation across a range of ...

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In Design Compiler you can use the command all_high_fanout -nets to obtain a collection of nets that has a fanout value bigger than high_fanout_net_threshold variable, which you can review using the command report_app_var high_fanout_net_threshold. A specific threshold N can also defined using the command: all_high_fanout -net -threshold N The reported ...

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Dmitry Grigoryev took care of it already, but there are a few things I want to add, and since I can't comment... First, be sure you are also carrying out a complete simulation, including timings, not just a logic one. You mention a latch in your question, be sure you actually want it in your design, because it can be a source of problems which you won't ...

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Help yourself to Xilinx Libraries Guide. LDE is a "Transparent Data Latch with Gate Enable" described on page 681. This is way too broad to answer. Nothing. I believe it literally means "Multiplexer number 341". The synthesizer can't provide you with descriptive names: how is it supposed to know what this mux is for in your design.

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You can do this easily in SystemVerilog as you can declare a parameter that is an array and then select index of the parameter array inside the generate loop. Most simulation and synthesis tools already support this. If you need to stay in Verilog, you can pack values into a parameter and then select a slice of parameter module top_module (); wire ...

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