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7 votes
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Can a flip flop possibly work at over 800MHz?

Here is a D flip-flop spec'ed to operate at 40 Gbps. Setup and hold times are advertised as 4 ps. It consumes only about 750 mW. These are manufactured with a SiGe process, although I don't know ...
The Photon's user avatar
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7 votes

Is (BC + AD)<<16 equivalent to (BC << 16) + (AD <<16)?

They are equivalent. The width of all operands get extended to the size of the largest operand before any operation occurs. As long as the width of one of BC or AD is 16 bits wider than the value ...
dave_59's user avatar
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6 votes
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Is it possible to create a PLL purely in digital design, if so how?

This is definitely possible. It is called an all digital PLL. Instead of a VCO, you use a numerically controlled oscillator, or NCO. An NCO is basically just a counter, called a phase accumulator, ...
alex.forencich's user avatar
6 votes
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Techniques to develop software and hardware of a SoC in parallel

There are also companies that develop Software (SW) and RTL in parallel and in cooperation between SW and RTL developers. Such development is typically done in small iterations where each iteration ...
lasplund's user avatar
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5 votes
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Relation between RTL and Verilog modules

First of all, Verilog is a Hardware Description Language used to describe a collection of digital hardware, and a module is just a way of hierarchically ...
dave_59's user avatar
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5 votes
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How to debug combinational loop warning in Xilinx ISE

In a combinatorial block (always @* begin ...), you can't have an assignment statement in which the same signal appears on both the left and right sides. For ...
Dave Tweed's user avatar
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5 votes
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Including one module in another module with variable

You need to go back to basics. Verilog is a hardware description language, not a programming language. Your code is describing hardware. Let's see what your code is trying to infer: ...
Tom Carpenter's user avatar
5 votes

Are Verilog and VHDL Register Transfer Languages?

RTL is a style of coding where clocked elements are expressly implied. This is generally done because synthesizers are not generally designed to design state machines on their own. While they often ...
Cristobol Polychronopolis's user avatar
5 votes
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When to set defaults for VHDL generics

My thoughts It's good practice to always mention a default value to generic during entity declaration because it makes sure ...
Mitu Raj's user avatar
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5 votes
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Is it a good practice to put assertion statements into VHDL RTL code to aid in simulation?

Assertions are supported in VHDL at different severity levels (\$\color{red}{\text{Error}}\$, \$\color{blue}{\text{Note}}\$ etc). You may use it to validate different properties/specifications/...
Mitu Raj's user avatar
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5 votes

Multiplication in VHDL by a fraction

In the testbench, there are numerous values listed for same simulated time. From the language reference: The delay values supported with the after clause do not cumulate, but all relate to the same ...
greybeard's user avatar
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4 votes
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Common way of describing a "double-sided wait"

One example of such a bus is the AXI bus, which originated with the ARM processor, but is increasingly being used as a standard interface for FPGA IP in general. The two handshake signals are called ...
Dave Tweed's user avatar
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4 votes
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Assigning the different value to parameters in Generate block in Verilog

You can do this easily in SystemVerilog as you can declare a parameter that is an array and then select index of the parameter array inside the generate loop. Most simulation and synthesis tools ...
dave_59's user avatar
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4 votes

Quartus 10166 error: "Always_comb construct does not infer purely combinational logic"

It's a typo. In the GameOver state, you have load_dcard3 = 0 twice and don't assign to load_pcard3.
Justin's user avatar
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4 votes
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'1011' Overlapping (Mealy) Sequence Detector in Verilog

The error is caused by mixing the combinational State assignment block with the sequential output block. The combinational state assignment block and the sequential output block have different ...
Shashank V M's user avatar
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4 votes

'1011' Overlapping (Moore) Sequence Detector in Verilog

Your state variable is too small. You have 5 states, but your variable is only 2 bits wide. It must be at least 3 bits wide. Change: reg [1:0] PS,NS ; to: ...
toolic's user avatar
  • 6,975
4 votes

Are Verilog and VHDL Register Transfer Languages?

While previous answer doesn't directly answer the question, it provides a common understanding of how RTL should be read regarding digital design topics, at least according to my engineering and ...
megasplash's user avatar
4 votes

How to check if all the signals used have been reset in a VHDL process?

What tool do I use to ensure that all signals and variables used inside a process are assigned an initial value in the process, maybe when reset is asserted or maybe every clock cycle? Same as every ...
Marcus Müller's user avatar
4 votes

Reading a file in Verilog

To read integer values (positive and negative) in decimal format, you can use the $fscanf system function. Refer to IEEE Std 1800-2017, section 21.3 File input/...
toolic's user avatar
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4 votes
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Verilog generate block error

You cannot, and there is no need to put the cordic module instantiations inside an always block. ...
dave_59's user avatar
  • 7,812
3 votes

Relation between RTL and Verilog modules

One of the problems with many courses is that due to time pressure they try to teach concepts with problems that are too small to need those concepts. A design is basically a hierarchy of modules. In ...
Peter Green's user avatar
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3 votes
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High impedance in RTL Verilog

Unless you are using SystemVerilog, you cant declare a constant like that. Instead use the replication operator. {(WIDTH){1'bz}} is a ...
Tom Carpenter's user avatar
3 votes

Determine which clock has arrived first

Latch clock A on the rising edge of clock B. If the result is high then A arrived first. Of course this is assuming you have zero setup and hold times on the data inputs of your latches or that you ...
Andrew's user avatar
  • 6,902
3 votes

Implementing gravity in VHDL and VGA.

Between floats (difficult to implement, resource-hungry) and integers (not enough precision), there's an intermediate: it's called fixed point math. Fixed point isn't much more difficult than integers ...
dim's user avatar
  • 16k
3 votes

Timing warnings for functional model

Setup and hold timing checks only make sense with post-layout information. A century ago, you could do timing analysis without layout structural information because the the device delays were ...
dave_59's user avatar
  • 7,812
3 votes

Will the High-Level Synthesis (HLS) design approach for FPGAs reduce the demand for RTL designers?

Eventually, the compiler more or less wiped out the assembly programmer. But it took a long time, and there are still a few paid ones about, optimising high speed functions to the Nth. There are more ...
Neil_UK's user avatar
  • 162k
3 votes

Will the High-Level Synthesis (HLS) design approach for FPGAs reduce the demand for RTL designers?

At the very least, people involved in development of those HLS tools will have to know how they work and thus understand RTL in details. Just like with general programming nowadays, when you have ...
Dmitry Grigoryev's user avatar
3 votes
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What is the difference between a hard module and a softmodule in RTL verilog code?

Soft cores are standard logic modules, written in Verilog or VHDL. They are called 'soft' because they are implemented in the re-programmable logic of the FPGA. You can edit and modify a soft module ...
Chris Fernandez's user avatar

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