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3 votes
Accepted

Constraining combinatorial path delays in Intel Cyclone-V FPGA

Your clock constraints look fine. Your delay constraints look fine as well. min/max constraints are not working That's not what you should interpret from the Timing Analyser's report. You asked for \...
Mitu Raj's user avatar
  • 11k
3 votes

SDC Constraint for reset synchronizer

My constraints now look like this: ...
Juergen's user avatar
  • 151
3 votes

How to constrain a clock signal out from a multiplexer

If the clocks are asynchronous (to each other), there are no meaningful constraints you can place between them. You need to create a constraint for clk_out that ...
Dave Tweed's user avatar
  • 175k
2 votes
Accepted

Constraining synchronous clocks at different frequencies in VHDL

The reason for the weird 0.05 is that your period for the 32MHz clock is 31.25ns not 31.2ns. ...
Tom Carpenter's user avatar
2 votes

How to estimate timing contraints for FPGAs?

As your FPGA and micro-controller run of different clocks, there is NO timing relation between them. To safely transfer data between them you have to use synchronizers or a circuit which has clock ...
Oldfart's user avatar
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2 votes
Accepted

Different output delays for internal to output and input to output path

Ideally, I want to set_output_delay only for paths from internal FFs to ulpi_dir, but it only supports targets, not sources? Yes, it's possible in SDC. You can use the ...
Mitu Raj's user avatar
  • 11k
2 votes

Constraining simple design

Looks like your tool is showing only the critical path, i.e., the one with the worst slack. There must be specific command/option to see detailed timing report which shows all timing paths. By the way,...
Mitu Raj's user avatar
  • 11k
2 votes

create_generated_clock quartus for derived clock

\$1\$ \$\text{Hz}\$ is a very slow clock, hence it's much much relaxed timing for setup, and meeting timing is not big issue here. You can constraint this slow clock correctly using ...
Mitu Raj's user avatar
  • 11k
2 votes

FPGA-centric timing constraints

Source-synchronous signals {clock, data} have to be routed with minimal line-to-line skew. You can specify a window on allowed skew variation between these two traces and prove the timing on FPGA. ...
Mitu Raj's user avatar
  • 11k
2 votes
Accepted

Basys 3 FPGA 7 segment display output delay

There is no need to time those paths as there are no clocked synchronous elements with setup/hold requirement at the destination. You can either disable the timing of such paths using ...
Mitu Raj's user avatar
  • 11k
2 votes
Accepted

Proper way to make HDL and timing analyzer understanding the clock slowdowns

TL;DR; Don't know about other tools, but for Quartus specifically, the answer is basically no, it can't figure it out for itself. Or perhaps rather it won't, it's pessimistic by design. The "...
Tom Carpenter's user avatar
1 vote

Timing constrain the ADC to FPGA data path

I do not think the overall architecture is the best one. How I would do it: clock ADC from the FPGA output pin, ADC to return back the data and clock (strobe) for FPGA to sample the data, synchronize ...
Anonymous's user avatar
  • 7,120
1 vote
Accepted

In an FPGA, is the input port delay related to the output port delay in the previous block?

As explained by @gotchi85 in the comments, input/output port delays apply only to FPGA boundaries. In other words, B1 and B2 would be different devices in the example above (being the FPGA one of them)...
Martel's user avatar
  • 1,259
1 vote

Pin vs Port terminology in SDC

A port is nothing but pin of the top-level design. The constraint set_driving_cell is used ...
Mitu Raj's user avatar
  • 11k
1 vote

Does synthesis/ PnR tool need create_generated_clock constraint for clock MUX output?

No, generated clock constraint is not needed, because the mux is expected to NOT change the period/phase of the clock, but just feeds forwards one of the input clocks based on the select signal. ...
Mitu Raj's user avatar
  • 11k
1 vote
Accepted

Use SDC format for timing constraints on Xilinx CPLDs

AFAIK, you can only use .sdc files with Synplify synthesis, not with ISE synthesis. If you're using ISE synthesis, then you'll have to find or create a way to translate .sdc to .ucf or .xcf I've never ...
Dave Tweed's user avatar
  • 175k
1 vote

How to correctly constrain a clock network with lots of mux branches?

Quite tricky and a bit complex. What I would have done is (SDC Contraints): Constraint clocks src_1 to src_N using: ...
Mitu Raj's user avatar
  • 11k
1 vote

SDC Constraints for digitally noise filtered CLOCK and DATA inputs

You have a logic clock of 50 MHz and a 1 MHz synchronous serial input consisting of CLK2 and DATAIN. The function of the serial clock CLK2 is to indicate the timing for DATAIN as it travels across the ...
TonyM's user avatar
  • 23.4k
1 vote
Accepted

SDC constraints for reusable component

You can specify SDC commands inside of your VHDL code with ALTERA attributes. The PoC Library is using this to apply relative timing constraints for synchronizers: ...
Paebbels's user avatar
  • 3,957
1 vote
Accepted

FPGA proper SDC constraint for hsync pulse

Synchronize and edge detect the hsync input with something like this: ...
alex.forencich's user avatar
1 vote

Understanding timing constraints

Open the TimeQuest Timing Analyzer by choosing Tools > TimeQuest Timing Analyzer. Choose File > New SDC file. The SDC editor opens. Type the following code into the editor: ...
Cristian Mardones's user avatar

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