4
votes
Accepted
ASIC timing constraints via SDC: How to correctly specify a multiplexed clock?
Define divide by 1 clocks on the and_* nets and declare them to be physically exclusive. Cadence RTL compiler handles the situation correctly by generating 3 timing paths for registers clocked by ...
- 430
3
votes
Accepted
Constraining combinatorial path delays in Intel Cyclone-V FPGA
Your clock constraints look fine. Your delay constraints look fine as well.
min/max constraints are not working
That's not what you should interpret from the Timing Analyser's report. You asked for \...
- 10.8k
3
votes
3
votes
How to constrain a clock signal out from a multiplexer
If the clocks are asynchronous (to each other), there are no meaningful constraints you can place between them.
You need to create a constraint for clk_out that ...
- 169k
2
votes
Accepted
Constraining synchronous clocks at different frequencies in VHDL
The reason for the weird 0.05 is that your period for the 32MHz clock is 31.25ns not 31.2ns. ...
- 63.8k
2
votes
How to estimate timing contraints for FPGAs?
As your FPGA and micro-controller run of different clocks, there is NO timing relation between them. To safely transfer data between them you have to use synchronizers or a circuit which has clock ...
- 14.2k
2
votes
Accepted
Different output delays for internal to output and input to output path
Ideally, I want to set_output_delay only for paths from internal FFs to ulpi_dir, but it only supports targets, not sources?
Yes, it's possible in SDC. You can use the ...
- 10.8k
2
votes
Constraining simple design
Looks like your tool is showing only the critical path, i.e., the one with the worst slack. There must be specific command/option to see detailed timing report which shows all timing paths.
By the way,...
- 10.8k
2
votes
FPGA-centric timing constraints
Source-synchronous signals {clock, data} have to be routed with minimal line-to-line skew. You can specify a window on allowed skew variation between these two traces and prove the timing on FPGA. ...
- 10.8k
2
votes
Accepted
Basys 3 FPGA 7 segment display output delay
There is no need to time those paths as there are no clocked synchronous elements with setup/hold requirement at the destination. You can either disable the timing of such paths using ...
- 10.8k
2
votes
create_generated_clock quartus for derived clock
\$1\$ \$\text{Hz}\$ is a very slow clock, hence it's much much relaxed timing for setup, and meeting timing is not big issue here. You can constraint this slow clock correctly using ...
- 10.8k
1
vote
Timing constrain the ADC to FPGA data path
I do not think the overall architecture is the best one.
How I would do it:
clock ADC from the FPGA output pin,
ADC to return back the data and clock (strobe) for FPGA to sample the data,
synchronize ...
- 6,908
1
vote
Accepted
In an FPGA, is the input port delay related to the output port delay in the previous block?
As explained by @gotchi85 in the comments, input/output port delays apply only to FPGA boundaries. In other words, B1 and B2 would be different devices in the example above (being the FPGA one of them)...
- 1,215
1
vote
Pin vs Port terminology in SDC
A port is nothing but pin of the top-level design. The constraint set_driving_cell is used ...
- 10.8k
1
vote
Does synthesis/ PnR tool need create_generated_clock constraint for clock MUX output?
No, generated clock constraint is not needed, because the mux is expected to NOT change the period/phase of the clock, but just feeds forwards one of the input clocks based on the select signal. ...
- 10.8k
1
vote
Accepted
Use SDC format for timing constraints on Xilinx CPLDs
AFAIK, you can only use .sdc files with Synplify synthesis, not with ISE synthesis. If you're using ISE synthesis, then you'll have to find or create a way to translate .sdc to .ucf or .xcf I've never ...
- 169k
1
vote
How to correctly constrain a clock network with lots of mux branches?
Quite tricky and a bit complex. What I would have done is (SDC Contraints):
Constraint clocks src_1 to src_N using:
...
- 10.8k
1
vote
Accepted
SDC constraints for reusable component
You can specify SDC commands inside of your VHDL code with ALTERA attributes. The PoC Library is using this to apply relative timing constraints for synchronizers:
...
- 3,907
1
vote
Accepted
FPGA proper SDC constraint for hsync pulse
Synchronize and edge detect the hsync input with something like this:
...
- 40.7k
1
vote
How to use simple generated clock in Verilog Code Vivado 2015.2
Constraints file is only used to apply various constraints on the design.
But the code which generates 50 MHz clock needs to be written by you.You can use a frequency divide by 2 code
...
- 96
1
vote
Understanding timing constraints
Open the TimeQuest Timing Analyzer by choosing Tools > TimeQuest Timing Analyzer.
Choose File > New SDC file. The SDC editor opens.
Type the following code into the editor:
...
Only top scored, non community-wiki answers of a minimum length are eligible