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5

I/Os of the top-level block are called port, I/Os of the subblocks are called pin. So get_ports and get_pins commands must be used accordingly. If the main clock is an input of the top-level block, get_ports is the appropriate command. For example: create_clock -name CLK [get_ports clock_main] ... Since clock_1 and clock_2 are the inputs of the subblocks, ...


4

Define divide by 1 clocks on the and_* nets and declare them to be physically exclusive. Cadence RTL compiler handles the situation correctly by generating 3 timing paths for registers clocked by cpu_clk (one path each for one clock). Registers directly driven by clk0, clk4 and clk_ext have their own timing arcs. create_generated_clock -source [get_ports ...


4

I'd say that the rule of thumb is: set either input port of the top module, or Q pin of an internal flip-flop as the source of generated clock. Example Verilog code: module top ( input clk, input rst, ... ); ... always @(posedge clk or negedge rst) begin if (rst == 1'b0) div_2_clk = 1'b0; else div_2_clk = ~div_2_clk; end ... ...


4

It is not an 'error' to sample data from one clock domain in another. Quartus will not prevent you doing it at design entry/synthesis stage. When you later run timing analysis with quartus_sta you will find that the register path between the two clocks (if truly different) is unable to make timing. You are running timing analysis, right?


4

Put clocks in different clock groups. This allows them to have the same phase and frequency yet be considered asynchronous for timing analysis. For a Quartus II .sdc file you would use this syntax: create_clock -period "100 Mhz" -name {CONF_CLK} [get_ports {CONF_CLK}] create_clock -period "100 Mhz" -name {PCIE_CLK} [get_ports {PCIE_CLK}] create_clock -...


3

I usually synchronise my async reset through a delay line of a few flipflops (relying on the FPGA configuration to have cleared them), and only use that synchronised reset (even if I'm using it as an asynchronous reset). In Xilinx-land, the tools can trace the timing through from the clock used in the delay line to the reset input (either sync or async) ...


3

My constraints now look like this: set_max_delay -to [get_pins -nocase -hierarchical s_rst_sync_ff[*]|CLRN] 10.000 set_max_delay -from [get_cells -nocase -hierarchical s_rst_sync_ff[*]] -to [get_cells -nocase -hierarchical s_rst_sync_ff[*]] 2.500 Besides, I enabled synchronizer identification in the Quartus qsf file: set_global_assignment -name ...


3

There is a -regexp option for get_posts. Try: set_input_delay -clock [get_clock clk] 5000 [get_ports -regexp data_x\[\d+\]\[\d+\]\[\d+\]] You can get bus ports by their base name. Not sure it it works on multi-dimensional arrays. So this might also work: set_input_delay -clock [get_clock clk] 5000 [get_ports data_x]


3

If the clocks are asynchronous (to each other), there are no meaningful constraints you can place between them. You need to create a constraint for clk_out that represents the "worst case" for any of the possible clock inputs, and use that to evaluate the rest of the design. The rest of the design must also be able to handle the timing violations that will ...


3

The reason for the weird 0.05 is that your period for the 32MHz clock is 31.25ns not 31.2ns. Alternatively you can specify the period as: create_clock -name external_clock -period "32MHz" [get_ports e_clk] However it is not as easy as just specifying the clocks, you will also need to constrain the interfaces so that Quartus knows what setup/hold times it ...


2

Synchronize and edge detect the hsync input with something like this: reg hsync_reg = 0; reg hsync_delay_reg = 0; wire hsync_posedge = hsync_reg & ~hsync_delay_reg; always @(posedge clk) begin hsync_reg <= hsync; hsync_delay_reg <= hsync_reg; end Then count the pulses of hsync_posedge with something like this: reg [7:0] count_reg = 0; ...


2

No, these constraints don't mean that OUT1 has to transit in that timing window. The output delay is modelling the delay between the output port and an external (imaginary) register. Delay of the path through OUT1 can be thought as follows. t_total_delay = t_clk-to-Q + t_comb_delay + t_output_delay - t_clk_skew The maximum value of t_output_delay (1.4 ns) ...


2

The all_registers command can be used to get a collection of sequential cells. The basic use of it is not different from all_inputs and all_outputs commands. The 4 timing reports may be generated as follows. report_timing -from [all_inputs] -to [all_registers -data_pins] report_timing -from [all_registers -data_pins] -to [all_registers -...


2

Constraints file is only used to apply various constraints on the design. But the code which generates 50 MHz clock needs to be written by you.You can use a frequency divide by 2 code wire clk_50MHz; always @(posedge clk_100MHz) clk_50MHz <= ~clk_50MHz; But to let xilinx know that this clk_50MHz is not a normal signal,you need to let xilinx know that ...


2

As your FPGA and micro-controller run of different clocks, there is NO timing relation between them. To safely transfer data between them you have to use synchronizers or a circuit which has clock domain crossing logic built-in like an asynchronous FIFO with a read and write clock (Every FPGA vendor I known has IP for those). This also means that you can't (...


2

Since we know the phase relation, those clocks are synchronous. The only thing we need to do is telling this relation to the synthesis/STA tool. create_generated_clock -source clk1 -edges {2 3 4} -combinational [get_pins pll/clk2] I would use the -edges option to define the phase. The following waveform explains the edges. Basically clk2 rises at the 2nd ...


1

You can specify SDC commands inside of your VHDL code with ALTERA attributes. The PoC Library is using this to apply relative timing constraints for synchronizers: architecture rtl of sync_Bits_Altera is attribute ALTERA_ATTRIBUTE : string; -- Apply a SDC constraint to meta stable flip flop attribute ALTERA_ATTRIBUTE of rtl : architecture is "-name ...


1

Open the TimeQuest Timing Analyzer by choosing Tools > TimeQuest Timing Analyzer. Choose File > New SDC file. The SDC editor opens. Type the following code into the editor: create_clock -period 20.000 -name osc_clk osc_clk derive_pll_clocks derive_clock_uncertainty Save this file as my_first_fpga_top.sdc (see Figure 1–38).


1

You have to learn all constraints used in SDC, from here. As you aware of all clocks frequency, so you just need to understand importance of each constraints and find out what optimum value should be correct. Some constraints like set_input_delay and set_output_delay has standard value or generalized value like, INPUT_DELAY_MARGIN is 60% of your clock ...


1

You could always just use the enable line on a DFF instead of mucking about with the clock frequencies and perhaps forcing the a signal not routed to be a clock to be used as a clock. Count the 100MHz pulses, and every time it hits 2 (or any divider), turn another signal on. This other signal then enables your DFF. This way you have your stable 100MHz clock ...


1

This command is used to prevent a clock network from being modified or replaced during optimization. It is Design Compiler command which is used during RTL synthesis. set_dont_touch_network [get_ports scan_enable*] it tells the DC to get all scan_enable* ports and also all the cells & nets that are also connected with these ports and then set ...


1

The tool assumes that clocks are rising-edge aligned, I believe, unless you otherwise specify them. That's why the tool doesn't complain.


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