# Tag Info

20

Most 8 bit CPUs have 16 bit address buses allowing them to address 64kbytes, precisely because 256 bytes really isn't enough to do very much! It just means they need to load two bytes instead of one, each time they need to load an address. Slightly slower but tolerable considering their size. (And yes there are many exceptions, mostly developed when 64k ...

9

Memory cells are arranged in a matrix This is a 16-bit memory, 1 bit wide, so it needs 4 address lines to address each individual bit. That's the a3..a0 lines at the left. a0 and a1 enter the green 2-to-4 demultiplexer. An N-input demultiplexer can have 2$^N$ output lines, and the binary input indicates which of those will be active. That's the row ...

8

The address bus and data bus are separated so they may have different sizes. For any specific address bus sizes there are a lot of techniques to address more memory than the register bit width The most common way is increasing the address bus width somehow by using multiple registers for the address AVR has R26..R31 that can be paired into 16-bit X, Y and ...

8

If we have a classical flip flop (like this image from wikipedia): You can see that depending on the state this is in, there is constantly some current flowing (and "stealing" current through the R3/R4 path, thus shutting that one off). The result then is never changing again, as long as VCC is active, thus the state of the whole apparatus is static. If you ...

7

Databus lines (pins) and address lines (pins) are completely separate. Simply put, databus lines determine maximum number of bits that can be transferred one at a time (and stored on the memory) whereas address lines determine maximum number of memory "cells" that can be selected. It was mostly a marketing thing that 32-bit x86 CPUs couldn't address more ...

7

Nearly all 8-bit processors have some ability to form a 16-bit address from a low-order part and a high-order part. On some processors including the original 8080, there are registers dedicated to holding the upper and lower part of an address (although from a programmer's standpoint there may be some registers like the 8080's stack pointer which don't ...

7

Unless your microcontroller has a direct bus support for interfacing to DDR/DDR2/DDR3 type RAM or your microcontroller is interfaced through an FPGA which has been programmmed to provide the RAM interface then it is likely that futzing around with DIMMs is not a useful exercise. There are several strong reasons why this is the case.... 1) DDR memory chips ...

7

16k x 9 means that the memory chip has a total of 16k locations in which it can store a binary number that consists of 9 bits. It will have a 14 bit address structure (14 bit gives you 16,384 locations in decimal). It may be a serial device but the address lines will still be there but internal to the device.

7

To put the comments into the form of an answer so that the question can get closed... The SDRAM part linked to is a 512Mx16 device, 512M addresses, 16 bits wide giving a total of 8Gbits. The DIMM linked has a capacity of 8GBytes, 8 times the capacity of the individual memory chip. The DIMM also lists its speed as PC1600 with timings of 10-10-10. For the ...

6

Some single data rate (SDR) SDRAM can be run at slower rates - check the Clock Period (max) spec. However, you have to issues refresh commands on a regular basis, and if you clock at 1MHz you might find you have no time for anything else! DDR SDRAM typically has a minimum (yes, minimum) clock frequency in the high tens of MHz... and the physical interface ...

6

Perhaps I can add a little simple information. As I understand it, POD (Pseudo Open Drain) drivers, have a strong pulldown strength but a weak pullup strength. A pure open-drain driver, by comparison, has no pullup strength except for leakage current; this is why the term "pseudo" is used. The remaining pullup strength is provided by parallel-terminating the ...

6

No fundamental reason why not. Synchronous SRAM is truly random access, fairly inexpensive, and easy to interface to. Its downside in that it occupies a fairly narrow niche between the on-chip BlockRam (not much smaller, free until it forces you to select a larger chip, massively parallel and more flexible) and external DRAM (massive storage capacity at a ...

6

256K x 8 means 256 kibi-locations, each location holding 8 bits. There are 18 address lines (218 = 256 * 1024) and 8 data lines.

6

Inside the SDRAM chip, the actual CAS latency requirement is a combinatorial time delay, independent of the external interface's clock period. It may help to think of it as an old-fashioned asynchronous DRAM chip "wrapped" in a synchronous interface. Since the bus master (CPU) can choose the interface clock speed, it makes sense to also allow it to ...

6

Can I use a DDR chip on a non-DDR controller? No. Is it crazy to attempt to add 512MB of external SDRAM to a STM32H7? It's just barely possible, but probably not worth the trouble. The largest SDRAM parts available are 512 MBit (not MByte). They can be configured as 64M x 8. Four of these in parallel can operate as a 64M x 32 = 256 MB memory; two banks ...

5

... get a better VLSI book? It's possible; it's just not optimal. Logic processes are designed for speed; they go to great lengths to avoid stored charge, adjusting doping, bias voltages etc to clear it away as fast as possible. Since stored charge is rather important to DRAM, the DRAM process is tuned in a different way! Thus while a fast logic process ...

5

The type of memory you need is SDRAM. It is not the same as DDR SDRAM. I don't think I've seen a Cortex-M device that supports DDR memory yet. You would typically go for Cortex-A family, if you need that kind of capability. You can easily find SDRAM chips on digikey or any other distributor site. At this point, the rest of you question is probably ...

5

SDRAM is indeterminate at power-on. So many models will randomize content to help expose errors coming from assuming that the power-on state will be determinate.

4

From the outside, each memory chip is organized as 1M words of 1 bit each, which means that it takes 20 address bits to specify a word. Internally, the memory is physically organized as a square matrix of 1024 rows and 1024 columns, with one bit in each position in the matrix. There are at least two reasons that the physical organization is important to ...

4

We're talking about an SODIMM module here. It has multiple chips on it, and has an overall format of 1G (230) locations of 64 (26) bits each. (Total of 236 bits.) The module contains 16 (24) chips that contain 4G (232) bits each. (Total of 236 bits.) The memory in each chip is organized as 8 (23) banks, each with 64K (216) rows and 1024 (210) columns of ...

4

It looks like you're doing most of your development on the actual hardware. In some cases it makes sense to do this, but this is not really one of those cases as complete functional models should be available for the SDRAM chips. I would highly recommend locating a functional model for either the specific chip you're using or a very similar one and doing ...

4

A 200 MHz DDR chip has a maximum bus bandwidth of 400MT/s. It does not mean it can transfer data constantly at that speed. The commands what to read are also sent on this bus, and the requested data is available after the latency period. When the data is available, a block of data can be transferred at full 400MT/s rate. Usually the maximum memory speed is ...

3

SDRAM is actually a very good choice for image processing, because both the capacity and the bandwidth (especially with DDR) are improved relative to SRAM. Coupled with using the FPGA's on-chip SRAM as line buffers, it allows pretty much any whole-image computation (including the 2D FIR you give as an example) to be pipelined to the point where you can ...

3

It's often true that there is some relationship between addressable memory size and internal register size, though the relationship varies for different reasons. 256 bytes of address space was considered too small even in the very early days of microprocessors, so most eight bit processors produced 16 bit (two byte) addresses, which addressed 64 kilobytes. ...

3

You can do a little better than this; because burst transfers only use the data paths while in progress, you can overlap bursts with address signal transfers. So you can get ready to transfer the next burst while the current burst is in progress; likewise you can open the next bank and set RAS for it before the current bank's transfer is done. Start the ...

3

Other answers have measured how RAM works internally, but they haven't yet mentioned how it is fits into a system. The simplest type of RAM to understand is a static asynchronous RAM. Such a device has a number of address pins, a number of data pins, and some control pins which together have three states of interest: Idle state, in which the signals on ...

3

A simple RAM can be expressed as (From some note):- RAMs are organised as square arrays of individual bits. There are two decoders, a row and a column decoder, and each one bit memory cell is only enabled when both its row and the column lines are one. In the case of a 256 bit RAM each decoder transforms a four bit binary number into a sixteen bit ...

3

This is one of those situations in which you're going to want to set up your logic analyzer for synchronous sampling (external clock) rather than asynchronous sampling (internal clock). Connect the LA's external clock input to the SDRAM clock signal. This way, each sample on the LA will contain one word of data from the SDRAM's data bus. Yes, it's true ...

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