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11

The address bus and data bus are separated so they may have different sizes. For any specific address bus sizes there are a lot of techniques to address more memory than the register bit width The most common way is increasing the address bus width somehow by using multiple registers for the address AVR has R26..R31 that can be paired into 16-bit X, Y and ...


8

If we have a classical flip flop (like this image from wikipedia): You can see that depending on the state this is in, there is constantly some current flowing (and "stealing" current through the R3/R4 path, thus shutting that one off). The result then is never changing again, as long as VCC is active, thus the state of the whole apparatus is static. If you ...


8

What you are describing is a direct memory access (DMA) operation. It looks like the Teensy 4.1 uses an NXP MIMXRT1062 processor, and that processor does have a DMA engine -- but in order to work for you that DMA engine would have to work with parallel data in, and would have to be otherwise compatible with the ADC you're proposing to use. Unless there's ...


8

In principle, this looks like of especially older acquisition devices worked. Practically, you're still facing a few core problems with your SDRAM: It's non-trivial to work with SDRAM; you must make sure that for the duration of your acquisition, you can count up addresses at 80 MHz, as well as that the SDRAM is able to accept new data every clock. Usually, ...


7

16k x 9 means that the memory chip has a total of 16k locations in which it can store a binary number that consists of 9 bits. It will have a 14 bit address structure (14 bit gives you 16,384 locations in decimal). It may be a serial device but the address lines will still be there but internal to the device.


7

To put the comments into the form of an answer so that the question can get closed... The SDRAM part linked to is a 512Mx16 device, 512M addresses, 16 bits wide giving a total of 8Gbits. The DIMM linked has a capacity of 8GBytes, 8 times the capacity of the individual memory chip. The DIMM also lists its speed as PC1600 with timings of 10-10-10. For the ...


6

256K x 8 means 256 kibi-locations, each location holding 8 bits. There are 18 address lines (218 = 256 * 1024) and 8 data lines.


6

The type of memory you need is SDRAM. It is not the same as DDR SDRAM. I don't think I've seen a Cortex-M device that supports DDR memory yet. You would typically go for Cortex-A family, if you need that kind of capability. You can easily find SDRAM chips on digikey or any other distributor site. At this point, the rest of you question is probably ...


6

Inside the SDRAM chip, the actual CAS latency requirement is a combinatorial time delay, independent of the external interface's clock period. It may help to think of it as an old-fashioned asynchronous DRAM chip "wrapped" in a synchronous interface. Since the bus master (CPU) can choose the interface clock speed, it makes sense to also allow it to ...


6

Can I use a DDR chip on a non-DDR controller? No. Is it crazy to attempt to add 512MB of external SDRAM to a STM32H7? It's just barely possible, but probably not worth the trouble. The largest SDRAM parts available are 512 MBit (not MByte). They can be configured as 64M x 8. Four of these in parallel can operate as a 64M x 32 = 256 MB memory; two banks ...


5

SDRAM is indeterminate at power-on. So many models will randomize content to help expose errors coming from assuming that the power-on state will be determinate.


4

From the outside, each memory chip is organized as 1M words of 1 bit each, which means that it takes 20 address bits to specify a word. Internally, the memory is physically organized as a square matrix of 1024 rows and 1024 columns, with one bit in each position in the matrix. There are at least two reasons that the physical organization is important to ...


4

There is a type of DRAM which includes an onboard refresh controller. It allows for large memory densities while allowing an MCU without a DRAM controller to treat it like an SRAM. It is called Pseudo SRAM, PSRAM, or Cellular DRAM by various vendors. An example example part number would be... Winbond W968D6DAGX7I, 256 M-bit, 133MHz, $3.89 on Digikey.com ...


4

You'd have to set up synchronization registers across the clock boundaries. And as the clocks are out of phase with each others, there's always the possibility of metastability, but I suppose the FPGAs are not very susceptible to metastability. I would suggest to run your CPU at some "easy" multiple of 9 MHz, perhaps 9 x 4 = 36 MHz or 9 x 8 = 72 Mhz and ...


4

We're talking about an SODIMM module here. It has multiple chips on it, and has an overall format of 1G (230) locations of 64 (26) bits each. (Total of 236 bits.) The module contains 16 (24) chips that contain 4G (232) bits each. (Total of 236 bits.) The memory in each chip is organized as 8 (23) banks, each with 64K (216) rows and 1024 (210) columns of ...


4

It looks like you're doing most of your development on the actual hardware. In some cases it makes sense to do this, but this is not really one of those cases as complete functional models should be available for the SDRAM chips. I would highly recommend locating a functional model for either the specific chip you're using or a very similar one and doing ...


4

To answer the first question, yes, you can. You'll have to use multiple DMA operations, and most DMA controllers have some means of "chaining" operations together for continuous operation. I don't have the specific details about how that works on the STM32. The CPU will probably have to process an interrupt at the end of each DMA block. To answer the second ...


4

Modern DRAM such as SDRAM, DDR ... DDR4 have an "automatic self refresh mode" where the memory just need to be powered to internally manage periodic refresh cycles. The rest of the computer can be powered down to save energy. In that mode, DRAM draws about half the normal idle current and 1/5 to 1/10 of the current drawn during reads. (DRAM refresh period ...


4

A 200 MHz DDR chip has a maximum bus bandwidth of 400MT/s. It does not mean it can transfer data constantly at that speed. The commands what to read are also sent on this bus, and the requested data is available after the latency period. When the data is available, a block of data can be transferred at full 400MT/s rate. Usually the maximum memory speed is ...


3

This is mostly dependant on the SDRAM you are using. For example, take a look at the Application Note TN-46-08: Initialization Sequence for DDR SDRAM. Also, I have found that the initialization sequence is not so strict. Usually you will stick with whatever is provided already and modify it according to your specific needs. If it doesn't work already, you ...


3

I would choose the right option for ease of assembly. One sided will also be cheaper if you go to larger scale manufacturing. The only reason I'd pick the left option would be size constraints.


3

I will answer this question specifically for the AVR controllers you mentioned. The basic principle also holds true for many other 8-bit architectures. AVRs are 8-bit cores. This means they have 8-bit Registers. However, 8 bits are not enough to access a usable amount of memory. Therefore, the AVR core is able to use a specific set of registers combined as ...


3

Make sure you keep the association with the byte enables correct. There should be no issue with switching around data lines within each byte or mixing up the bytes, so long as you keep track of the byte enables. However, it would be a good idea to check the datasheet to make sure there aren't any odd requirements with respect to bursts or accessing ...


3

Well, you're never going to get that exactly. That's the theoretical max bandwidth. However, you can get pretty close. DRAM is set up so that rather large blocks can be read out sequentially with no wait states. Well, you might need some wait states to set it up and a few to move to the next block, but within the block it will transfer at the full rate. ...


3

The key element in the difference is redundancy. A DRAM has to be perfect (that is, it has no redundancy). This is because, in order to get the speeds required of DRAM, there is no buffer level between the address inputs and the memory cells except for address decoding. Flash, on the other hand, is not expected to run nearly as fast as DRAM, and this allows ...


3

You could get a Raspberry Pi. That would simplify a lot of things that you want to achieve.


3

DIMMs have 64 single ended data lines, and they will be divided up among the chips - say, 8 chips with 8 data lines each, or 16 chips with 4 data lines each, or perhaps on a small module you could have 4 chips with 16 data lines each. Super high density modules may even have 32 chips with 2 data lines each. Each data line will be connected to only one of ...


3

So search for DRAM on wikipedia. The concept comes directly from the core memory that preceeded it (look that up too). You had ferrite bead cores that were arranged with row and column wires, and a sense line. You could energize a single core using a specific row and column and using the right hand rule cause a magnetic charge in one direction or the ...


3

A very crude description of SDR SDRAM is here. In fact there is very little difference between the earlier Single-Data-Rate and modern Double-Data-Rate memory in terms of control. SDRAM is a pain simply because you have to write a controller which has to handle access of the memory in terms of sequencing read and write commands, refreshing the memory, ...


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