Just because you can find a different, and what seems to you easier, way to detect a toy sequence, doesn't mean that state machines are dead, or that you shouldn't do the exercise you've been set. Celebrate your creativity, it's good to think of alternatives, but work on the state machine solution as well.
It's frequently not clear to students that any ...
You're right, you can implement any sequence detector that way.
But that means that if your sequence is \$N\$ bits long, you'll be doing
\$N\$ 1-bit comparisons
a logical AND of \$N\$ comparisons every time step
every time step. The first point means you need \$N\$ flipflops, the second and third means you need \$N\$ gates for the reference ...
The other answers are correct, but what they haven't mentioned is that your solution is a state machine. It has one state for every possible combination of the most recent \$N\$ bits, which means there are a total of \$2^N\$ states.
Explicitly constructing a state machine to match only the particular sequence of interest results in \$N\$ states, which can ...
You need to come up with a state diagram (your very first step) that actually does what you want, before going through all of the detailed logic design.
With a Moore-type machine (outputs associated with states), it requires 5 states to recognize the sequence and then output a "1". Then, you need to replicate 2 of the states in order to output a "1" for a ...
Yes, the one hot method.
For a state diagram of N states, use N d-type flipflops and a code that has N - 1 zeroes and a single 1.
When you are in S0 then the S0 flipflop has a '1' in it. It is hot.
This method has the cost of needing one flipflop per state but does allow design by inspection rather than needing to draw up lots of tables. The method has ...
Your approach can't always look back far enough
There are sequences a simple state machine can detect which your approach cannot. For example, a 1, followed by any even number of 0s, followed by a 1.
Your approach could detect 1001, 100001, 10000001, but it can't do the general case. This is because you can only examine a finite amount of history. ...
Signal (non clock) assignments in a testbench should generally be non blocking (<= operator). Clock assignments should be blocking (= operator). Otherwise there's a race condition.
There are probably exceptions to this rule, but it works for me. Beyond that you need a good understanding of the verilog simulation phases. This rule of thumb will work for ...
I'd suggest a more general approach (without counters) that needs some more gates but is much easier to understand and to debug and it can be adapted for more complex patterns.
Drawn as classical logic gates:
The VHDL implementation is very straight forward:
implement a 32-bit shift register
check whether output vector equals reference vector
As user W5VO♦ said, it was a matter of changing data on a positive edge. The solution was simple, all I had to do was to move slightly my input signal, so it would be registered on the next rising edge (poor explanation, but I hope everyone knows what I mean). Final outcome looks like this:
Your regs are defined wrong.
reg presentState ;
reg nextState ;
reg [1:0] presentState ;
reg [1:0] nextState ;
By default, regs only have 1 bit so only states a and b can ever be reached.
Also, you should do your testbench a bit differently. Try
@(posedge clk); sequence <= 1'b1 ;
@(posedge clk); ...
Got to admit, for that I would be very tempted to ignore the FSM approach all together, in favour of something like a 5 bit shift register and some simple combinatoric stuff, easier to write, easier to READ (Arguably more important) and very, very obvious in just about any HDL.
5 flipflops and at most one or two LUTS, which is I suppose your second option.
You get a phase sequence indicator. There are two kinds, one uses a small 3-phase motor and it rotates in one direction or the other. The second kind does it electronically. They start at well under $100.
You should not attempt to connect an oscilloscope or an electronic grade DMM to the mains, especially 3-phase mains, unless you have the proper equipment,...
You state machine coding is rather weird.
You normally start with looking which state you are in and then respond to the input to go to a new state. Also you should give your states better names.
2'b00 : next_state = SEEN_00;
2'b01 : next_state = SEEN_01;
2'b10 : next_state = ..
2'b11 : next_state = .....
This is a overlapping sequence-detector for the required sequences,i used this website to draw the FSM.
This is the code i have written to draw it
The issue is due to the line number 67, as u are using synchronous mode of asserting the reset it takes 2 cycles to show its affect on the outputs. if u write it in async assertion
always@(posedge Clock_L or negedge Reset_L)
then it would have taken single cycle .. please use synchronizers if u are using the push button to reset ur code as it might lead ...
I think the problem lies in this part
always @(posedge CLK)
if (Reset_L==0) SCURRENT <= A;
else SCURRENT <= SNEXT;
In your Moore machine you set the 'z' in the combinatorial section. At the same time as you set the state to C. Thus the two coincide. To get z high after two bits have been detected (thus after the state C) you must move the assignment into the clocked section:
z <= (state==C) ? 1'b1 : 1'b0;
// or even shorter:
z <= (state==C);
Your Mealy machine is ...
The answer is 3.
You are actually counting a sequence of 8 states. So you need 3 bits... = 3 flip-flops.
The values 0,1,2 and 3 are taken from the 2nd and 3rd bit of the counter. You ignore the first "bit".
Or if you prefer, you can refer to the first stage as a clock divider "/2" for your two bit counter.
State machines can be simple or can get to be ...
This isn't really a sequence detection problem. All you need to do is remember the previous state of each input (two DFFs). The rest is combinatorial logic on those bits combined with the current value of each input (four 2-input gates).
Either I am missing something, or this is pretty straightforward.
Look at the diagram below. when the second 1 gets clocked in, your output switch to 0, and stays 0 until you reset the circuit for the next sequence. If no double zero appear in the stream, output stays 1.
simulate this circuit – Schematic created using CircuitLab
You are probably going to be ok because the base voltage will be only one diode drop above ground, and the base-collector junction, with the similar voltage drop, will have a small voltage, if any, due to the reverse bias and the current is limited by your base resistor. However, best practice would be to consider an opto-isolator here and keep V+ ...
From what I understand, the voltage you've labeled V+ will remain on, even when +5 disappears.
This is an issue, because current will be able to flow through the base-collector junction of the transistor, and then through the ESD diodes of the micro, trying to power it. It may or may not be enough current to cause damage or turn on the micro, but it's ...
Let me suggest an approach.
First off decide if you want to adopt a Moore or Mealy representation. A Moore machine will generally have more states and the outputs depend only on the state register value. A Mealy machine has conditional outputs, where the output logic functions are functions of both the state register value and the inputs to the state ...
Yes, the 6 states should be 000, 001, 010, 011, 100, 101, 110. 000 represents the beginning, 001 represents when you have recognized '0', 010 for '00', 011 for '001', 100 for '1', 101 for '10'. When the input is 0, it should always point to state 001; also, from state from 011, it should point to 001 with output of 1. When the input is 1, it should always ...
Recognizing a sequence of symbols is known as "lexical analysis", or more colloquially, "scanning" or "lexing". It's actually a huge topic in software, where an input grammar needs to be broken into meaningful tokens as efficiently as possible. There's a whole process that involves writing a formal grammar for the sequences to be recognized, converting that ...