14
votes
Accepted
In FPGAs, is it safe to execute non-blocking assignments like `b <= a; a <= 0;` in the same clock cycle?
Yes, you should get the same behavior in an FPGA as you do in simulation, assuming the Verilog code looks something like this:
...
- 8,771
13
votes
Accepted
Why can't I make flip-flops in logic simulators?
Because from this page, the style that you show only works if the width of the clock pulse is tuned to be long enough for the output stage to react, yet short enough for the thing to not oscillate. A ...
- 46.7k
13
votes
In FPGAs, is it safe to execute non-blocking assignments like `b <= a; a <= 0;` in the same clock cycle?
While I can't get into the heads of the original designers of Verilog, I suspect that 99% of engineers who use it will tell you that your code snippet exemplifies the whole point of non-blocking ...
- 46.7k
12
votes
How is the Q and Q' determined the first time in JK flip flop?
The JK flop can power up in either state. With perfectly matched gates, the odds would be 50-50 for each state. It is up to the rest of the system to initialize to a known, desired state, or to not ...
- 56k
12
votes
Why can't I make flip-flops in logic simulators?
The circuit you show is a gated JK latch, not a flip-flop. It suffers from a flaw: with T high and clock high, the cross-coupled NAND gates form a ring oscillator. This is sometimes called the ‘race-...
- 56k
10
votes
How is the Q and Q' determined the first time in JK flip flop?
When power first comes on, this can't be understood as a digital circuit. To the actual physical circuit, inputs and outputs can be between 1 and 0, or even beyond. Part of designing logic primitives ...
- 4,907
6
votes
Accepted
How to know if a verilog code is sequential or combinational?
This will synthesize to sequential logic. If b is 1, then output will become 01. Consider ...
- 76
6
votes
Accepted
Are Verilog if blocks executed sequentially or concurrently?
Sequentially. Statements within an always block are evaluated sequentially, doesn't matter if blocking or non blocking assignments are used - nonblocking assignments are simply deferred assignments, a ...
- 41.5k
6
votes
Accepted
Why I am getting one clock cycle delay in Verilog case statement?
At the positive edge of clk you change from WAIT state to SERVE state. You don't change the ...
- 68.8k
6
votes
Accepted
How can flipflops sense the edges of the signals?
The SN74HC74 datasheet shows how a flip-flop (here also with set/clear inputs) is implemented:
These boxes are transmission gates, i.e., 1:1 switches like those in the SN74HC4066. Please note that ...
- 19.7k
5
votes
Does combinational and sequential logic correspond to some mathematical logic systems?
Is it correct that the functionalities of digit circuits are divided into combinational logic and sequential logic?
Yes. And sequential logic in digital electronics is subdivided into asynchronous ...
- 2,331
5
votes
Why can't I make flip-flops in logic simulators?
To implement an edge triggered T Flip-Flop that does not rely on gate delay timing, requires, I believe, a minimum of 6 Nand gates. The circuit below simulates fine in CircuitLab.
simulate this ...
- 26.1k
5
votes
Accepted
Design of non-overlapping "1010" sequence detector
After detecting "1011", why does the detector go back to B
The diagram is correct for the non-overlapping sequence. To get into state D requires the sequence 101. If the next input is 1 (...
- 8,771
5
votes
How can flipflops sense the edges of the signals?
The simplest answer from some point of view is that a flipflop can be thought or being just two latches one after another.
The data passes throuh from input through the first latch when enable is low, ...
- 164k
4
votes
Are Verilog if blocks executed sequentially or concurrently?
In Verilog the statements inside the if... begin end are treated as concurrent if the code in them uses non-blocking assignments. They’re sequential if blocking assignments are used. So if the ...
- 56k
4
votes
Power strip with individual time delays for each socket
You are looking for a power sequencer.
There are many brands that make them:
Panamax, Furman, Pyle...
- 8,191
4
votes
Why I am getting one clock cycle delay in Verilog case statement?
The other answer directly answers your question about the relative timing of your output signals, and it also provides an astute observation of a probable bug in your code (...
- 8,771
3
votes
Accepted
3-Stage Shift Register using Blocking assignment in Verilog - Differences among simulators
You din is changing at the same time as the clock edge. This is a race condition and as such the behavior of the simulator is not defined.
This is because you use ...
- 14.5k
3
votes
Sequential circuit: What does state mean exactly?
The number of states in a sequential system is not determined by the number of inputs, and it is not determined by the rows of a combinational truth table. Just talking about the "state" of the inputs ...
- 31.6k
3
votes
Accepted
How to design Gray code synchronous counters of large widths using SystemVerilog?
The design is partitioned into 2 parts - one for combinational logic and another for sequential logic.
In the sequential logic part, an always_ff block is used. Counter is an internal signal used to ...
- 2,331
3
votes
Does combinational and sequential logic correspond to some mathematical logic systems?
Logic is logic. There are certain stylized "logics" like "first order logic" which are constraints on the expressivity. "Temporal logic" or "modal logic" but in ...
- 1,551
3
votes
Accepted
Question on timing diagram of a SR Latch with different gate delays
The problem is caused by what is known as the Inertial Delay Model used by HDLs like Verilog and VHDL. The output of a continuous assignment or primitive gate cannot change faster than its propagation ...
- 8,715
3
votes
How can I output a sequence of bits using only simple discrete components?
If this were 1978, the solution to your problem would be to use one 8-bit preloadable shift register or two 4-bit preloadable shift registers, a 555 and some sequencing logic. You'd set the shift ...
- 46.7k
3
votes
Accepted
Is Quine–McCluskey algorithm globally optimal or is there a better way for K-Map reduction?
Is Quine-McCluskey the best possible, most optimal way of doing that?
Yes. It is - it's a more machine-palatable way of doing it vs. Karnaugh maps that are mostly targeted for humans.
The problem is ...
3
votes
In Sequential Circuit, Are Two States Equivalent If Their Next States Are Each Other?
In Sequential Circuit, Are Two States Equivalent If Their Next States Are Each Other?
In general, no. If two states are equivalent, then starting from either state, if the circuit is fed with ...
- 26.1k
3
votes
Accepted
Timing parameters of sequential circuit - digital electronic
Your statement on \$T_{cQ,bb}\$ is correct. Take your operating conditions into account for minimum and maximum. You might need them for the next stages.
Operating conditions include commonly load, ...
- 3,406
3
votes
Interaction between multiple blocking assignment and non-blocking assignment running in separate procedural blocks in Verilog
The recommended Verilog coding practice is to always use non-blocking assignments to describe sequential logic. This means that assignments to signals inside an ...
- 8,771
Only top scored, non community-wiki answers of a minimum length are eligible