20

The problem is keeping the signals on a parallel bus clean and in sync at the target. With serial "all you have to do", is be able to is extract the clock and as a result the data. You can help by creating lots of transitions, 8b/10b, bi-phase or manchester encoding, there are lots of schemes (yes this means you are adding even more bits). Yes, ...


16

The shift is from "parallel on a single clock" to "multiple serial links". Such as PCIe, where a card may have 1x to 16x "lanes". There are two factors involved, skew and size. Adding more connectors makes both the cable, its connectors and the receptacles on each device larger and more expensive. Look at how large things like Centronics printer cables and ...


15

Why is the serial connection faster than the parallel connection? You're making wrong assumptions. Take any serial connection. Now place 10 in parallel and call that the parallel version. Which one is faster ? So how come the serial connection is considered the future while the parallel one as a thing of the past? Says who ? Parallel connections are ...


13

Given your available options, it appears that you do have some pins available: SPI is full-duplex and requires 1 clock + 1 data each direction + 1 optional chip select = 3 pins CAN is half-duplex and requires 2 data for bidirectional comms = 2 pins USB is half-duplex and requires 2 data for bidirectional comms = 2 pins TTL Serial is anything you want, but ...


10

But I wonder how does this handshaking takes place between a Master and Slave when the Slave is sender and the Master is receiver and only the Slave (sender) knows when there is no more data to send to the receiver? This isn't supposed to happen. i2c is a very defined protocol and each slave device should be known to each master. Typically, the master ...


8

the more conventional 4 to 20 mA More conventional is a very relative term, and it seems you might be coming from a process control background, where sensor signals are often processed and converted to a current internally in the sensor. Let me assure you that it's not the most common thing in the world. What's the advantage […] rather than […] ...


5

I've never used CAN bus so I can't comment on that. Which leaves SPI, I2C, TTL serial and USB. TTL serial is usually clocked at 115,200 baud, but many microcontrollers can run it at 1 Mb/s or higher. You'll have to check your microcontroller's datasheets and see if you can run it that fast. Obviously both ends must match. The advantage for TTL serial is ...


5

Maxim has an application note titled 1-Wire Search Algorithm: The strategy is too involved to accurately describe here, but the basic principle is based on: 1-Wire is an open drain bus: multiple devices can pull the bus to GND simultaneously. 0s are encoded as long low pulses, 1s as short low pulses (by actually not pulling the bus low). If multiple ...


5

First, the technocal answer: For one, USB3 and SATA both use thin stranded twisted pairs (USB3 spec states to mak the cable 'as thin as possible', with 26-34 AWG given as example). 10GbE uses four solid relatively thick twisted pairs (23 AWG minimum). The thicker and solid strands create a larger surface area which in turn means lower resistance to high ...


5

There are standard RS422/RS485 transceiver ICs available Here you'' find many pages of RS485 related ICs at Digikey You can use standard asynchronous serial data using RS485 if desired. "Rolling your own" multistation code should not be too hard [tm], but it's an oft invented wheel - there will be many people already offering software (much for free) that ...


5

Since most logic and microprocessor IC's use edge clocked timing, it's when the transitions from 0-1 and 1-0 occur that are important to timing. The high and low parallel lines simply tell you that a line may be high or low but not some indeterminate level such as tri-state). In your case shown, greyed out means not valid data/address (multiple signals), not ...


5

Let's get some things straight first, to avoid miscommunication. 1) There is no "negative voltage line" in RS-485 specification. All the negative voltages in various guides and documentations refer to differential output of the line driver. The lines themselves (usually named A, B or Y, Z) swing between ground and positive voltage (standard +5V, but low-...


4

For backward compatibility with PATA/ATA/ISA, SATA uses the PATA/ATA/ISA command set. PATA/ATA/ISA is simplex because it is a connector to the ATA/ISA/PC/XT bus which is simplex. The ATA/ISA/PC/XT bus was simplex because it was a connector to the 8086/8088/80286 processor data bus, which was simplex.


4

It is a simple enough matter to "bit bang" a pair of the IO pins of a parallel port to emulate a serial port. It's all in the software. And that's where it all gets a bit tricky. The basic operations of reading and writing are simple enough - what is hard, when you are working on a PC with an OS in the way, is the precise timing needed to read and write ...


4

In avionics (particularly flight safety critical) it is not unusual to see the usual comms (SPI, I2C) within a box, but externally it is usually going to be ARINC 429 (civil) or MIL-STD-1553B (Military) to / from sensors. There are others such as STANAG 3910 which is used on Typhoon. Within a system that communicates between boxes (not aircraft level) it ...


4

Serial ports exist in both synchronous and asynchronous forms. I2C is synchronous but the more familiar UART serial is asynchronous. Both have their own advantages. Synchronous serial ports allow for arbitrary timing, while asynchronous ports require precise timing but use less connections.


4

The biggest drawback to this system I can see is that if the slaves are all power cycled for some reason they will all collide when trying to join the network in the grace period. This means it may take a very long time until they all rejoin the network. If you have a limited number of potential addresses (say 256) the master can always poll a ...


4

You haven't explained what exactly your listing shows, but it might be the message ID, followed by the number of data bytes in brackets, followed by the actual data bytes. Nothing seems to be explicitly stating whether the IDs are 11 or 29 bit. Perhaps just by using 3 HEX digits for the ID this listing indicates 11 bit IDs. If so, it would show 8 HEX ...


4

CAN was designed to be a bus, not a star topology network. Because of this non standard configuration it might be difficult to get the speeds that you want due to reflections, but because of the short line length of 2m, each line could be considered a drop, and the recommended limit for drops at 1Mbps is 2m. Source: Elektromotus CAN bus topology ...


4

Etherenet is based on CSMA/CD, which signifies carrier-sense multiple access with collision detection. It's not single master, any device can send and recieve independly, like multi master / multi slave, so that's why collisions happen. In such case the message sending is repeated, for both devices that had collided but each has it's own random timer, so ...


4

Any communications channel that is multiplex means it can be accessed by more than one transmitter. That's pretty general; in your context it means that different transmitters can use it at different times. A bus master is the piece of hardware that actually controls who has access to the bus. So a multi-master bus is one that has a mechanism for multiple ...


4

Those are the two options. If slave receiver does not accept more data it can NAK the byte, but master is still responsible for sending the stop condition. For a slave transmitter, it can't signal anything to stop, it must be known beforehand, or it could be encoded in the data, e.g. text string is terminated with a zero so slave can transmit zeroes until ...


4

Let us say a Slave or Master is sending multiple bytes to the receiver on I2C bus and the number of bytes is not defined before hand. So then how will the sender tell the receiver that it has no more data to send? If Master is the sender, then he knows how many bytes have to be sent. Master will signal the end of his data transfer by sending a STOP ...


3

It is a Phase Lock Loop which takes an accurate 100Mhz reference clock distributed over the connection, and multiplies the frequency to modulate data at extremely high speeds, almost exactly the same as RF transmissions do for things like common Wifi Signals (2.4GHz), except via a high speed serial bus. There is some interesting info on page 3 of this app ...


3

SPI peripheral inside a general purpose microcontroller (AVR, or PIC, or MSP40, etc) is hardwired to a large extent. It is what it is. Transaction stop sequence is formed by the CS# line. Want to use a non-standard SPI-esque communication format with framing bits? I think, it would be safe to assume that there isn't a general purpose microcontroller (μC) ...


3

Well, there are a lot of possible solutions... but you haven't given enough information really on what the communication looks like between the test computer and the subsystems. Is this entirely up to you on what to implement? I'm going to assume it is, but the solution would probably change if the protocol over RS485 is already defined or selected. Most ...


3

You need to interface the RS422 properly to the Arduino. There are special chips that do this for you. Just like you would use a MAX232 (or similar) to interface the Arduino to an RS232 system, you need to shift the voltages to the right levels, and create or combine the differential pairs. Maxim (the makers of the MAX232 chip) make a number of chips for ...


3

The idle state is defined as 1 (for TTL serial), and here's why: Let's say you have a data line with two states, represented by two voltages. For simplicity's sake, you choose 0 V and 5 V to represent 0 and 1 (TTL serial, for example). Now, this voltage is present on a wire between a transmitter and a receiver. When we choose the idle state as 1, if the ...


3

To summarise the discussion and respond to your test results: it seems that the XS201A has an undocumented 4 bits of line drive after which the driver is disabled Agreed, that behaviour fits with what I have seen before on some converters, and thanks for running the test. It is likely to be a relatively fixed time that the line is actively driven after ...


3

Wikipedia has an article with a list of x86 CPU sockets by year. Check it out: as CPUs became faster, their interface sockets grew from a mere 40 pins in the 1970s to 1500+ pins now. This cannot be explained by word width alone: if 40 pin socket was sufficient to fit a 16-bit CPU, surely a 64-bit CPU of a similar design should fit in 160 pin socket. The ...


Only top voted, non community-wiki answers of a minimum length are eligible