7

Try .option plotwinsize=0 Always good to try when you get weird waveforms like that. Likely compression/sampling issue.


6

Welcome to the wonderful world of FPGA simulation. Yes, simulations take a long time. Running for a full second is a lot of simulation. One trick you can do is speed up your blink rate just for the purpose of simulation, say to 100 Hz. Then you'll be able to verify your code oscillates correctly in a mere 10ms simulation. Once it works, change back to 1Hz ...


5

F = 200 MHz or T = 5 ns is the fastest clock in your design and it looks like you don't have any events in your design to be captured at 100 ps precision. You can run simulation with a precision of 500 ps instead of 100 ps, since your Test bench needs to drive clock edges at 2.5 ns. This may speed up the simulation. But the difference may not be noticeable ...


4

Now, it's the same as your original drawing.


3

I'm measuring the input and output power in this manner:... The multimeters are used to measure the input and output voltage and current, the product block is used to multiply voltage and current and get the instantaneous power and the RMS block (fundamental set to 20kHz, which is the switching frequency) is used to get a steady value. That's not how to ...


3

If what you have is a .step and you're measuring the same quantity (e.g. V(out)) then you can use .meas to measure the value of interest at that particular time, then plot the stepped data: Here {C} is parameterized and used with a .step command. The .meas command measures V(o) when the time is 9 ms. Then the error log can be opened up (CtrlL with the ...


3

It looks like the Schichman-Hodges model (LEVEL 1) calculates the output resistance as: $$ ro = \frac{1+\lambda V_{DS}}{\lambda I_{D}} $$ This fit with the simulation results: $$ ro = \frac{1+(0.04V^{-1})(3.411V)}{(0.04V^{-1}) (30.7 \mu A)} = 925.439 K\Omega $$


3

The assumption is that your input signals (reset and strobe_in) are synchronous to the clock. You should drive those signals in your testbench similarly to how they are driven in the design. Use @(posedge clk) instead of using # delays, and use nonblocking assignments (<=) instead of blocking (=). A clean way to do this is to use repeat loops to count ...


3

If you are using blocking assignments, it's better to trigger the stimulus in the negedges to avoid race conditions at rising edge. For that purpose, you can change your clocking: reg clk = 1; always #1 clk = !clk; Otherwise, in your current code, there is a race between different procedural blocks at instant #10. The events are: The stimulus strobe_in ...


2

Blocking statements are being used in the testbench for strobe_in. So strobe_in_q gets the updated value during counter=6 itself. In non-blocking statements, all the variables in the LHS are evaluated in parallel just like in a real circuit. Try something like this # 1 reset = 1; # 2 reset = 0; # 10 strobe_in <= 1; # 2 strobe_in <= 0; # 10 $finish; If ...


2

You are right about the opamp being unable to instantly change its output potential. The reason for this is mainly parasitic capacitance and inductance present at every point in every circuit. Choose any two points in a circuit, and those two points will have some amount of capacitance between them, which makes it impossible for potentials at either point to ...


2

Take a look at this: - The input changes 1.5 volts and the output changes by about 25 volts hence, the slop of the line is the gain of the amplifier. But, if when you made you hysteresis graph the XY speed was plotted in microseconds (rather than seconds) then rise-time, fall-time and propagation delay will all cause the slope to be flattened.


2

You can use a simple voltage source and set it to PULSE-Mode. There you can specify rise and fall time. In order to make it a ramp the Ton[s] and Tperiod[s] must be 0. If you add some parameters it looks like this: Just copy and paste: voltage source: PULSE({Vmin} {Vmax} 0 {1/f-tfall} {tfall} 0 0 0) parameters: .param f=32 tfall=30u Vmin=-3.3 Vmax=3.3 If ...


2

Research the LTSpice PWL (piece-wise linear) volage/current source. In that source, you define a series of data points [time,voltage]. Interpolation between points is linear, so you'd need one point at time 0 (-3.3v), another at 1/32Hz (+3.3v), another at 1/32Hz + 20us (-3.3V), etc.


2

What you are trying to do is somewhat misguided. Just because free space has an 'impedance' doesn't mean that it is a suitable port for a scattering matrix. Ports for a scattering matrix have well defined incident and reflected waves (think coax cable, waveguide, or an idealised circuit theory port of two wires), there is no single wave that you can use ...


2

Whether or a freespace mismatch generally reflects is not defined – imagine this: you put a high-resistance, very thin cable that's got nothing to do with the wavelength into free space. It's not well-matched to free-space impedance at the frequency you care about at all! But it will not reflect very much; the fact that mismatches reflect is something that ...


2

In the circuit below, focus on C1 and R1 to understand the differentiator behavior: Assuming \$V_z\$ always zero, \$\frac{dV}{dt}\$ at the capacitor is \$\frac{1V}{10ms}\$, so: \$I_c = C \frac{dv}{dt} = 100 nF * \frac{1V}{10ms} = 10 \mu A\$ Considering this current goes only through R1: \$V_{out} = -10\mu A * 100k\Omega = -1V\$ R2 and C2, with such small ...


2

To illustrate the difference between OP and @pat 's solution, I exported the waveforms as text. Here are the first fifty points. Without the plotwinsize=0 option, these points span several cycles as shown in the red with a jagged appearance. EDIT File details: Without the option, 20154 lines With the option, 44360 lines


2

To mix two simulation paradigm (SPICE, VHDL) you need a package that supports both. These however are few and far between. SIMextrix is a SPICE simulator but can also accept Verilog HDL. One option is CO-Simulation permitting one simulation domain to communicate with another. Matlab for instance can simulate some SPICE parts and can co-simulate with ...


1

You can add a DC source in series with a ripple source and a noise source. The latter is a behavioral voltage source which can be found under components as bv. The advantage of separating B1 and V1 is that you can also assign an AC voltage to V1, so it will work in .ac analyses.


1

The derivative of a triangle is a square wave. The integral is something else that looks (sort-of) sinusoidal. So it's good it doesn't look square. Anyway, your integrator is saturating. That accounts for the output being at the supply rail. You can prevent that by paralleling the capacitor with a resistor (try 100K, but I'm not sure what op-amp model they ...


1

In the standard monostable circuit, the 555 triggers on the negative-going edge. With Vcc = 9 V, the Trigger input has to sit above 3 V in the idle state, then go below 3 V to trigger the output. But ... The 555 is not a normal monostable. If the trigger input still is low when the circuit times out (in around 2 s in your case), the output will stay high ...


1

All of these can be converted from one to another. Data formats Between dB and magnitude, a logarithmic conversion makes sense, although for S-parameters, I'd expect that 10*log10 be used instead. Between magnitude/angle and real/imaginary forms, the rectangular-polar conversions apply: real = mag * cos(angle) and imag = mag * sin(angle) in one direction; ...


1

In regular MOSFETs, which can conduct in reverse, the inductor current can pass through one of the MOSFETs during the deadtime. If you use bidirectionally blocking switches, then the inductor current has to collapse immediately after turn of, which induces a huge voltage at the switch node. An obvious remedy is the use of regular MOSFETs (or GaN FETs). ...


1

S12: The effect of the air (port2) on the feedpoint (port1): is it the same as S21? is an antenna considered a passive network? Yes, an antenna is considered a passive (and lossy) network, and it's reciprocal. Be very sure you take mental note of the fact that the reference impedances on both ports are different! S22: I'm not sure how to consider the ...


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