6
Your first circuit has a 3:1 voltage divider.
Your second circuit doesn't. The op-amp input impedance is so high that the 2k resistor makes no difference. It sees the full 1.5 V of the battery.
4
No, it's nothing like the same part. One is (more or less) an op-amp + reference, the other is a thyristor.
As far as I know there is no support in Falstad for adding SPICE models as in full-featured circuit simulators such as PSpice or LTspice.
3
Looks like you found a convergence corner case.
Cap directly connected to voltage source: Falstad detects the cap loop and says no.
Cap connected via ground: Falstad doesn't detect the loop, oscillates (what you're seeing.)
Cap connected via resistor to ground: Varies. Below 100 mohm, won't settle down. Above 100 mohm, converges.
Here's my sim (clicky here)...
3
LTspice (like most SPICEs) doesn't perform a .TRAN analysis with a fixed timestep, and that's because of the way the solver works. There are exceptions, though (e.g. see compumike's answer). But if you can tolerate an external utility, there exists one called ltsputil.exe. It can be found in the LTspice group (registration needed, to avoid spammers).
If you'...
3
250uW is the correct power in the first schematic. There is 0.5V across R1.
The second schematic shows a voltage follower with 1.5V across the R1 so again the reading is correct (ideally it would be 2.25mW but the op-amp is not ideal).
3
No, for an ideal op-amp, no current flows into the terminals so for a buffer circuit there is no current flowing through the resistor, therefore no power in the resistor. In fact, there is no voltage drop across the resistor at all because there is no current flowing through it.
I think you mistakenly thinking there is a virtual ground on at the inverting ...
2
In your first circuit, there is voltage division due to the two resistors. That voltage division is 3 to 1 and that means the power is reduced in R1 by 9 times compared to it not being divided.
So, if I divide the power from the op-amp (2.241 milli watts) by 9, I get 249 micro watts into R1 i.e. pretty much exactly what the first circuit is reported to ...
2
Your voltages are wrong. 24VAC is the RMS voltage, and LTspice uses peak.
LTspice has a pot component that allows you to set the shaft rotation from 0..1
And you have a short.
Either flip one voltage source or (better IMHO) add a phase shift phi of 180° to one of them).
2
You can use numeric literals together with the keyword AKO (A Kind Of) to step between .MODEL definitions, and numeric literals instead of names for .SUBCKT, but with certain conditions.
Example #1:
The name of Q1 is {x} which, because it's between curly braces, it will be evaluated. If it was simply x, it would have had to have a .MODEL X ... defined. The ....
1
Your scope connection is wrong. If you want to see the voltage of the cap, you need to connect the scope to both terminals of the cap.
Also note that you shorted the cap on the board (vertical holes are connected).
1
Using tips from both @a concerned citizen and @qrk I think I figured this out. I switched to LTSpice as it has a bunch of half bridge drivers already in the libraries and it just seemed easier to use. I went back and modeled the transformer as a coupled inductor with the leakage in series. This seemed to help some with the S1 current waveforms.
I used a GaN ...
1
In theory and reality if you know all the assumptions, there is no difference.
In practise , there is.
e.g. initial conditions, output impedance , trace inductance, path length, parasitic coupling, Cap ESR, inductor DCR, load capacitance, EMI ingress and egress , thermal properties, race conditions, tolerance stackup, voltage margins, thermal environment, ...
1
Any nonlinear transfer function will produce intermodulation a certain amount of sum and difference frequencies of two different input frequencies.
A single frequency will produce harmonics according to the order of power in the nonlinearity.
e.g.
BJT and FET current gains produce 2nd harmonics from quadratic effects (Ic vs Vbe).
Square waves are caused by ...
1
I think the question is intended to specify the initial capacitor voltage Vo=5 at t=0 and initial inductor current Io=0 at t=0. Your circuit, as drawn on the right, seems to keep the voltage at 5 forever.
This is easy to fix with a Time-Controlled Switch that opens or closes at t=0. In fact, we'll use two of them: SW1 to disconnect the voltage source, and ...
1
It's easy to get the data you're looking for with the embedded CircuitLab simulator:
simulate this circuit – Schematic created using CircuitLab
This is currently configured with a 5ms simulation with 1us time step. This time step 1us divides evenly into your function generator's period, 100us. As a result, you'll get exactly 100 samples per sine ...
1
For the options setting plotwinsize=0 to have effect on your simulation (that is, to disable window compression), you have to tell the simulator that you want to print at a constant time step. To do so, you should indicate the desired Tstep as a parameter in the .tran command:
*you've written down:
.tran 0 2 0 1e-9
*you should write:
.tran 1e-9 2 0 1e-...
1
Maybe add this to your circuit:
options plotwinsize=0
From LTspiceHelp:
1
Remove the dot at where the wires cross at the right of X5 - the dot indicates a connection between the wires, and you don't want a connection there.
A potentiometer is a variable resistor. It has three terminals - one for each end of the resistance element, and one for a sliding contact that moves along the resistance element. You have probably used ...
1
I know I'm necroposting but this is important for anyone in the future reading this: while including ".inc opamp.sub" will work if you're using the generic "opamp" from LTspice, this will NOT work with Opamp2, as OP was using in the image they posted. Opamp2 requires a user supplied model to function. If you want a generic opamp to use ...
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