10
votes
Common emitter transistor amplifier working in simulation but not in reality
Let's start with some simple calculations based only upon a few starting points:
\$R_{_\text{C}}=6\:\text{k}\Omega\$
\$A_v=100\$
\$V_{_\text{CC}}=12\:\text{V}\$
\$v_{_\text{PP(IN)}}=20\:\text{mV}\$
...
- 70.2k
4
votes
Common emitter transistor amplifier working in simulation but not in reality
It seems to me that with an emitter resistor of 60 Ω and a collector resistor of 6 kΩ you should get reasonably close to a gain of 100 without the 1470 μF emitter capacitor (C3). It's most likely that ...
- 384k
3
votes
Common emitter transistor amplifier working in simulation but not in reality
R2/R1 set the base of the transistor at about 0.81V above ground. This means there should be about 0.2V across R4, which means ~ 3mA collector current. So the 6k collector resistor would have 18V ...
- 59.1k
3
votes
Accepted
Can't find the Pspice model for a diode
I was wondering if someone with more experience could tell me how to
find the model for the diode or if some of them just can't be found
Spice models for dual diodes are much, much rarer than for ...
- 384k
2
votes
Accepted
2
votes
Can't find the Pspice model for a diode
You can use any sim with an ideal Sch. Diode with Rs=3.9 mΩ and add 2000 pF @ 0V varicap load. Even Falstad's can model this with Saturation current levels , series Rs and emission coefficient.
- 136k
2
votes
Common emitter transistor amplifier working in simulation but not in reality
Simply use the simulation probe or real scope probe at the transistor's collector to see its average DC voltage.
The top of the waveform is squashed with distortion which is normal at high output ...
- 2,377
2
votes
Accepted
"Tiny " XOR gate simulation not working
Why do you have all of your substrate connections tied to the transistor sources? All N-channel substrates should be "gnd" and all P-channel substrates should be "vdd".
Remember, ...
- 165k
2
votes
Do gate level simulations have any utilitly in the current highly complex digital circuit designs?
If you are doing an FPGA design I think that timing closure would be enough.
When you are doing custom silicon however I think the manufacturing and NRE costs justify doing a full gate level ...
- 7,658
1
vote
Common emitter transistor amplifier working in simulation but not in reality
For stable dc biasing it is typical to aim for at least 1 volt at the transistor's emitter. The larger the dc bias at the transistor's emitter then the smaller will be the dc emitter current changes ...
- 5,218
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