New answers tagged simulation
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What is the meaning of "e" in this timing diagram?
e is a numeric value displayed in hexadecimal format. It is the same as 14 in decimal. It means that bits in[3:1] are set to 1,...
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How to create a PWM source with fixed frequency and decreasing duty cycle (at some interval) in LTspice?
Probably brute-forcing a solution using a PWL source is the quickest way to a solution. It's very useful for weird and/or complex sources. Once you dabble in generating your own PWLs using a ...
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How to create a PWM source with fixed frequency and decreasing duty cycle (at some interval) in LTspice?
For an arbitrary stimulus in SPICE I write a program in some other language (I like AWK, you might prefer something else like Python) that writes an output file containing the definition of a PWL ...
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How to create a PWM source with fixed frequency and decreasing duty cycle (at some interval) in LTspice?
I'm not exactly sure what you want to do, but I might have a way to accomplish it that is unproven.
Look at the models for the LTC6993 (there are several with different features. They can do many ...
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Multisim simulation insight
If "j * omega" ... is an inductance ...
And 4*V is a "step generator" ...
Then I could write these equations: Made with Maple ...
i1 (left-high loop), i2 (left low loop), i3 (right ...
- 11.9k
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Qucs voltage divider tutorial: simulation error
You may click 'check DC bias' icon (it is next to simulate icon) to run your DC simulation and can get your node voltage.
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HSPICE command naming weirdness
make a new file with cover up the target models as below
it will solve the problems
...
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Why am I getting unknown states in output for Booth multiplier Verilog code?
When I run your simulation and trace the unknown outputs back to their sources, I see that the controller module has several signals which are unknown: ...
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Why am I getting unknown states in output for Booth multiplier Verilog code?
Looking in the controller module I can't see how state is given an initial value. I think that could then cause the unknown ...
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SIMPLIS - Buck CM from C. Basso Website
The circuits I provide in my 90+ ready-made templates are simplified versions of what a real controller would do. It is for clarity reasons, so that everyone can understand the operating flow, but ...
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SNR simulation and "desired output signal"
Audio equipment have nominal output levels. Recorders, amps and mixing devices have also nominal input levels. It's either dBV or dBm to the nominal resistive load. Use that nominal level as your ...
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SNR simulation and "desired output signal"
I see that audio equipment, like preamplifiers and audio recorders,
always indicate their SNR in dB. But in relation to what output
voltage?
Well, the audio company marketing people will always try ...
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How does periodic steady state analysis find the transfer function of switched capacitor circuits?
Question: "How does periodic steady state analysis find the transfer function of switched capacitor circuits?"
As to my knowledge, there are two methods which allow an analysis of SC ...
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When I try to simulate VHDL code, the signals do not work, losses, show a orange color
Apparently you try to simulate your logic without applying a clock signal. All your logic depends on the input clock. Therefore the outputs are necessarily all undefined (...
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Verilog output register not changing
What is causing this bug?
You have a simulation race condition. All the signals in your code change at the same time, which means the output signals may not display all the actual transitions in ...
- 6,780
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Time-varying capacitor generates higher than supply voltage? Capacitor power generators?
Yes, this is correct. I mean, I don't have the exact data of your waveforms, and I'm not going to run sample code just yet, but you seem to have the right method at least, which is encouraging.
For ...
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Method used for breaking the loop deemed unsuitable
Measuring loop gain by breaking the loop and using a different port seems... peculiar, to say the least.
Mind, such a method might garner upvotes when it's well enough written and not manifestly wrong,...
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Method used for breaking the loop deemed unsuitable
I am not sure if the setup as shown with the 2nd figure works correctly. It is a rather uncommon approch because the test signal is not injected into the opening point. My doubt: The node between R3 ...
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Understanding optocoupler's operation through simulation
Let's run a sim...
CTR looks very different from the datasheet (non saturated case):
Here's the model from LTSpice
...
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Understanding optocoupler's operation through simulation
The datasheet simply says CTR is 20% minimum and 50% typical. And that is at If=10mA.
Datasheet does not say what is the maximum CTR.
So if simulator result shows 70% CTR, it is within specification, ...
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Misunderstanding in sequential and combinational implementation, based on blocking or non-blocking behaviour
With the blocking assignment in the testbench (=), you have a simulation race condition.
The proper way to drive synchrounous inputs from the testbench in Verilog ...
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Reverse polarity protection and inrush current limiting - back to back mosfets
These MOSFETS will be all the time ON since you need 0V between Gate and Source (0 Vgs) (not higher than -0.6V according to the datasheet) to turn them OFF. Which means, in this case, that
the gate ...
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Error in OrCAD: circuit too large
This is a limit in the software you use. There's a fixed number of electrical components maybe 30-40-60 and in your schematic more components than that is used, so it shows this error. Try to update ...
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Voltage Doubler capacitance calculation
C3 and C4 are way too small. You will need more requirements for a complete design, but here is a start.
For C4:
\$ I = C \frac{dv}{dt} \$
\$ C = \frac{I \Delta t}{\Delta v} \$
For t = 1/2f (one half ...
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Is there a piezo element in the KiCad libraries?
The chances of finding a component like that in a built-in library are very slim, so I wouldn't hold out hope that another CAD program would be any better. However, KiCad makes it very easy to add new ...
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Is there a piezo element in the KiCad libraries?
Preface: Mac, PC, Linux, Kicad runs on them all.
If it's just the piezo symbol you're looking for, you can create a symbol quite easy yourself, or usually there are libraries and symbols on the ...
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What are some good replacement parts for the given circuit?
Stopping short of taking a close look at operation, I can still offer some observations on the building blocks.
Op-amp
The op-amp appears to be very ordinary; a uA741 would do, or even LM358, or a ...
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Compute diode model parameters from IV curve
I made a online tool to solve diode model parameters. It finds the three DC characteristics parameters (Is, Rs and N). Below is the screenshot.
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Contradiction between two circuit simulators in measuring open loop gain
Just tried now with microcap v12
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Contradiction between two circuit simulators in measuring open loop gain
I suspect the difference is due to the BJT models being slightly different between TINA and LTspice. The parameter values to compare would be those that determine the following static (DC) transfer ...
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Simulating cmos comparator on cadence virtuoso
You have not biased the comparator properly. An NMOS input pair comparator will need the reference voltage to be higher than VGS(M1)+VDS(M5). Since you've connected the reference to 0V, the comparator ...
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Why does the waveform simulation go wrong using structural D flip flop in Verilog?
But to answer your actual question, the problem is that your "structural" DFF isn't an edge-triggered FF at all -- it's just a latch.
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Why does the waveform simulation go wrong using structural D flip flop in Verilog?
I must make it in structural.
That is incorrect. You must question the reasoning behind that claim.
Using a structural model for sequential logic like a flip-flop is the wrong way to achieve what ...
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