# Tag Info

7

If your design is not a big commercial thing, I would be tempted to suggest not reinventing the wheel and go with a tried and tested design - especially if you are not sure yet about how the overall design will look The Papilio Pro board uses the same Spartan 6 FPGA, and its schematic is open source: (Image from here) In the past I've successfully ...

7

The warning you are seeing is most likely WARNING:PhysDesignFules:2410 - This design is using one or more 9K Block RAMs (RAMB8BWER). 9K Block RAM initialization data, both user defined and default, may be incorrect and should not be used. For more information, please reference Xilinx Answer 39999. I just got this warning myself a couple of days ago and ...

6

The materials declaration is used if your product needs to comply with RoHS or other regulatory restrictions on material content. RoHS not only requires that your product not contain certain materials, but also that you document this fact. Typically, in order to do that, you need to request the vendors of all the components in your design to provide a ...

6

When converting parallel data to serial data, you take a parallel bus running at low frequency, and then clock it out serially at a much higher frequency. Why doesn't it use different type modesules such as 10:1 Gear box ...? A "gearbox" is basically nothing more than a SERDES block, the only difference being that the output is typically multi-bit wide. ...

5

Your measurement is not correct. The duty cycle is measured at 50% ($\frac{1}{2}V_{dd}$). So measure again at 1.65 Volt, if $V_{dd}$ is 3.3V. The 'real' high and low times: - above 90% of $V_{dd}$ is high - below 10 % of $V_{dd}$ is low does not matter. If a circuit has special requirements for the clock or data signal, it defines rising and ...

5

If you know precisely what you want to end up with, there's no need to have Xst try to infer it from a behavioral model. You can instantiate a block RAM object directly in HDL code. Details on the appropriate syntax, and the options involved, can be found in Xilinx UG615: Spartan-6 Libraries Guide for HDL Designs, around page 274 ("RAMB16BWER"). You can ...

4

The additional feed-back ports (clkfb_*) are visible when you select something other than the default "Automatic control on-chip" for the "Clock Feedback Source" (Page 3 of Clocking Wizard, version 3.6). It has nothing to do with the selection of "No Buffer" for the input clock. If you just want to get a 50 MHz internal clock out of the 100 MHz external ...

4

You should absolutely worry about power sequencing... at least until you read the documentation and it tells you that sequencing is not required. In previous generations sequencing was more of a concern, but according to Xilinx DS162 "Spartan-6 devices do not have a required power-on sequence". Worry about ramp rates (DS162 Table 6), and sequencing in ...

4

You should download and use Xiinx' power estimation tool. With it you specify the various IOs, logic used, clock speeds, et cetera, and spits out an estimate. It is here: http://www.xilinx.com/products/technology/power/xpe.html

4

Nearly all I/O pins on nearly all FPGAs/CPLDs can be configured as either bidirectional, an input or an output. Without bidirectional pins, you couldn't implement bidirectional data buses for memory chips like RAMs and Flash EPROMs. The general case for the I/O pin interface buffer circuit within an FPGA is: an output buffer that can be tri-state or driving;...

3

Move the take lookup right next to the increment so the output is registered. That is a gigantic lookup table, though. You may want to consider using a compressed lookup table to save on the block RAM. The trade-off is you may need a couple of multipliers. Here is an example of a pipelined, compressed sine lookup table: https://github.com/alexforencich/...

3

Yes. There are ESD protection diodes to Vccio and these will turn on if the pin is supplied with a voltage higher than Vccio. It may be possible to add a series current limiting resistor and use the ESD protection diode is a clamp, but this is not recommended. You should look in to using some sort of external level shift circuit to prevent damage to the ...

3

The problem I see is you have declared count_max as a 1 bit wide wire and then assign a 32bit constant to it - this will essentially get truncated to 1 bit. This will then mean you are doing additions and comparisons between 32 bit and 1 bit values on line 29, thus you get the issue of it saying truncated 32bit down to 1bit. Then by extension your ...

3

Firstly, the supported coding styles are documented in the synthesis user guide. For Xilinx ISE, this would be the XST user guide. Page 200 and onward explains what is supported. Sadly it uses the old conv_integer function, but you are already using the newer numeric_std equivalents, and these will work just the same with XST. If you can find an older ...

3

Problems I see in your code: 640x480@60 uses a pixel clock of 25.175 MHz, not 25 MHz. The difference may be enough to keep some monitors from synchronizing. Consider using a PLL to generate the appropriate clock (50 MHz x72÷143 gives 25.1748 MHz, which is within 9 ppm), or targeting 800x600@72 instead, which uses a pixel clock of exactly 50 MHz. The ...

2

The memory read needs to be registered to be recognised as a block RAM: process(clk) if rising_edge(clk) then ctr <= ctr + 1; cos <= SINE_TABLE(to_integer(unsigned(ctr))); end if; end process; I would also make ctr of an integer type - then you don't need to faff around with the conversions.

2

Your count_next wire is implicitly declared. That means it is one bit wide therefor count[31:1] never get assigned and you never reach your max count which also needs to be declared as a 32bits rather than 1 bit as Tom pointed out. wire [31:0] count_next; localparam count_max = 32'd50000000; //you can use a wire but a parameter is a better description for ...

2

The absolute maximum input voltage for LVCMOS33 on spartan6 is 4.1V, anything higher than that (even for a short time) may damage your FPGA permanently. Check out the info on: Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Use a resistor in series or a voltage converter before connecting 5V source into any LVCMOS33 input of your FPGA.

2

I have had some first hand experience with the issue of the Xilinx Spartan 6 pins getting pulled up high during configuration at either power up reading from the initialization SPI flash chip or at programming time. Putting pull down resistors to overcome the onboard pullups can be problematic because in the normal operational mode the FPGA output pin has to ...

2

The memory is internal to the FPGA, you access it from logic programmed into the FPGA. So if you wanted to use an FPGA purely as a RAM chip then you would need to write the logic to interface the internal ram to the outside world. The pinout could be just about anything you wanted but using the global input buffers for clock/enable type signals would ...

2

A gearbox translates n bits of frequency a to m bits at frequency b. Thus, gearboxes translate from parallel data to parallel data. The ratio of bit translation and frequencies is $\frac{n}{m} = \frac{b}{a}$. Another gearbox implementation use the same frequency on both sides. In that case valid and ready signals are needed to throttle the bandwidth on ...

2

I am sampling an incoming signal, which is returned as a 10-bit value, can I evaluate that sample in a case statement and assign a result value for the output register based on every one of the 1024 cases? Would this eat up LUTs in the FPGA fabric? Yes, the syntax of Verilog allows this. Would this eat up LUTs in the FPGA fabric? It depends entirely on ...

1

This looks a lot like issues associated with not synchronizing all of your inputs into the main clock domain. You should always be running all of the input signals through flip-flops before you use them for anything. As for your 12.288 MHz clock out; use an ODDR2 element to drive it like so: ODDR2 #( .DDR_ALIGNMENT("C0"), .SRTYPE("ASYNC") ) ...

1

You will probably need to use a gearbox to re-pack the bits from whatever deserializer width makes the most sense. Altera has some example gearboxes in their cookbook, as well as some design techniques.

1

Welcome to the world of Xilinx :) The problem is known, and I don't think they maintain this app very actively and if you search for the Answer Record mentioned in the error list, you will see that it requires some changes in the example code to make it compile with newer versions of ISE. You can find the solution to your problem at: Discussion about the ...

1

The XAPP495 does not have any form of EDID handling. However, as you are using the Digilent Atlys board, and are having one HDMI input and one HDMI output, then as long as you use the correct HDMI ports, EDID handling becomes much simpler. Essentially you just need to pass the EDID signals from the output port (the one connected to your monitor) through to ...

1

If I understand your design correctly, I think you have a design issue that needs to be addressed first. You are grabbing data from one of several UART receive buffers and shovelling it directly into a UART transmit buffer. This will have the impact of mixing up bytes from each of the incoming buffers into the output stream with no apparent way of unmixing ...

1

Does this mean that the clk needs 18.826 to reach all clocked parts? It actually means, that the maximum delay of the combinational path between two FFs driven by that clock (or back to the same FF) is 18.826 ns. This delay is the sum of the clock-output time of the source FF, the delay of the combinational logic, and the setup-time of the destination FF. ...

1

Error in UCF file: NET "reset" LOC = C17 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; The pin reset is an input, so you shouldn't set a drive strength of 8 mA and a slew rate, these constraints are for outputs. Please check your schematic, if the reset pin / wire has already a pullup resistor. If so don't enable the internal pullup in the ...

Only top voted, non community-wiki answers of a minimum length are eligible