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Transmitting HDMI/DVI over an FPGA with no support for TMDS

Good questions. I have been researching this topic myself recently, and will try to provide some brief answers here. what exactly is TMDS vs LDVS? LVDS (low-voltage differential signaling) is ...
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7 votes
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Xilinx Spartan 3A programming connection : where are MISO and MOSI pins?

If you are expecting to be able to just use your programmer to load a configuration bitstream directly into the FPGA which only stores that in specialized SRAM, you are in for a surprise when it ...
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6 votes
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VHDL Delimiter Character

Since answers should be written as answers and not comments, I'll summarize here: IEEE Std 1076-2008, section 15.7 - String literals A string literal has a value that is a sequence of character ...
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4 votes

Xilinx Spartan 3A programming connection : where are MISO and MOSI pins?

For the XC3S50A-4VQG100C device you use the JTAG interface, not SPI. It has dedicated pins. JTAG is a somewhat similar interface to SPI but standardized for FPGAs, debug interfaces on many ...
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3 votes
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How to cross clock domains efficiently?

Assuming the data of interest changes on the falling edge of the 27Mhz clock and is sampled on the rising edge, the approach with minimal delay would be to have a divide-by-two clocked by the 27MHz ...
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3 votes
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VHDL latch for Xilinx Spartan 3E

If I'm understanding the second warning correctly, ISE would like you to give an explicit start value to some of your signals: ...
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3 votes
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Put a DAC at the output of FPGA

You need to work out what sort of specifications you need because DACs come in all sorts of varieties from the basic ladder network all the way up to very high speed ones. A cursory glance at Maxim ...
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3 votes

Does spartan 6 XC6SLX9 FPGA have an internal oscillator ? .If so how to access that?

Most FPGAs contain internal ring oscillators for managment purposes. Things like configuration loading on startup (where do you think clock for master SPI and master selectMAP comes from on Xilinx ...
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2 votes

Transmitting HDMI/DVI over an FPGA with no support for TMDS

TMDS uses CML (Current Mode Logic) that is terminated to Vcc at the receiving end. LVDS from the standard (IEEE644) is a voltage mode driver that is terminated across the pairs also at the receiving ...
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2 votes
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Spartan 6: How do I use my differential clock?

For constraints, do something like this: ...
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2 votes

How to give analog input from 3.5 mm jack to FPGA (Spartan 3e)

Two problems: The ADC is (I presume) 0 to 5 V. Your audio will be much less than this. The ADC accepts positive signals only. Your audio is AC (alternating current). The polarity alternates between + ...
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2 votes
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FPGA : program that doesn't work everytime

Does it work OK in simulation? If not, fix that first. You don't want to be debugging both logic problems and the weirder-only-sometimes-happens-real-world problems at the same time. Get a reset ...
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2 votes

FPGA : program that doesn't work everytime

Firstly you need to make sure your clock constraints are set up right and your design passes timing. You can get all sorts of strange behaviours from a design that fails timing. Ideally you would set ...
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2 votes
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How to remove the below error when doing FPGA implementation of program that use RAM using Xilinx block generator?

Xilinx's Spartan-3E only support RAMB16, RAMB16WE being a primitive of a later architecture (Spartan-3A, and maybe others). You most likely generated your IP with the wrong project options. Make sure ...
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2 votes
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How to probe into the internal signals and registers in FPGA without using JTAG?

One of the most useful ways to gain access to the internal register contents is to design it in!! First you have to decide the most convenient mechanism with which to access the FPGA. You could use a ...
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2 votes

royalty free embedded processor

I have heard a lot of good stuff about vexriscv. In general, there is a lot of work around the riscv instruction set, in terms of compilers, soft processors, and all sorts of ASIC implementations.
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2 votes

Why are All pins pull-up in SPARTAN 6?

There is a dedicated pin that defines whether there is a pull-up on all pins during configuration or not: HSWAPEN. The "Spartan-6 FPGA Configuration User Guide" UG380 contains all the ...
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1 vote

How to count pressed keys on FPGA spartan board

Mechanical switches bounce when they are pressed. Your software needs to debounce the key press before considering it valid. This typically consists of delaying 30-70 ms after the initial key press is ...
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1 vote

How to cross clock domains efficiently?

I couldn't exactly follow the entire scenario you described, but if the question just boils down to "what's a good way to pass a single clock cycle pulse into a different clock domain", considered ...
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1 vote

interfacing spartan 3 fpga with arduino motor shield

You connect the driver to the Spartan however you like. The L298P is a dual H-Bridge device and has the following block diagram: Without the exact motor board you are using it is hard to say how it ...
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1 vote

Unknown problem with I2C on Spartan 3-E {VERILOG}

The problem was with the hold time.Since the SDA line changed exactly on the falling edge of SCL, There was a hold time violation.I added a flip flop to produce a delay of around 600ns and the design ...
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1 vote

Verilog Error: System task finish is always executed

I was getting this problem too, the thing that was causing it for me was I was clicking the green arrow rather than right clicking "Simulate Behavioral Model" and selecting Run. The green arrow ...
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1 vote

Verilog Error: System task finish is always executed

So I installed ModelSim and that somehow convinced ISE to stop complaining about $finish. The weird thing is that I'm still not using a ModelSim simulator, it's ...
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1 vote

How do I reset my registers on Digital Clock Manager output?

I think your logic is correct, except you mean to implement an asynchronous reset .i.e the reset is independent of the clock. This doesn't reflect in the code above and can be fixed by adding the ...
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1 vote

HDMI (TMDS) output with Digilent Atlys - examples do not compile with ISE 14.7

Welcome to the world of Xilinx :) The problem is known, and I don't think they maintain this app very actively and if you search for the Answer Record mentioned in the error list, you will see that ...
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1 vote
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Problem with implementation XAPP495

The XAPP495 does not have any form of EDID handling. However, as you are using the Digilent Atlys board, and are having one HDMI input and one HDMI output, then as long as you use the correct HDMI ...
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1 vote

Benefit of using RAM, or some form of internal memory on a FPGA

The second part of your question (2D array vs. RAM) really comes down to the resources available on your FPGA. Usually storing something as large as an image or frame of video in logic elements isn't ...
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1 vote

Clock Forwarding Won't Work

I think you need an OBUF on the end of your ODDR. The ODDR cannot drive a pin directly. No doubt there is a warning in there somewhere, but hidden amongst thousands of trivial warnings :)
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