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12

I haven't done this for double precision FP, but the same principles apply as for single precision, for which I have implemented division (as multiply by reciprocal). What these FPGAs do have, instead of FPUs, is hardwired DSP/multiplier blocks, capable of implementing a 18*18 or (Virtex-5) 18*25 multiplication in a single cycle. And the larger devices ...


11

There's no reason to use FPGAs unless you need to. Even two similarly talented engineers in the MCU and FPGA fields would use an MCU for a relatively simple automation task. Pro MCU: MCUs usually have all the peripherals to the outside world ready to go Compiling takes seconds (FPGAs take minutes to hours) There are an order of magnitude (or two!) more ...


7

Good questions. I have been researching this topic myself recently, and will try to provide some brief answers here. what exactly is TMDS vs LDVS? LVDS (low-voltage differential signaling) is simply an electrical specification for a differential signaling interface, while TMDS (transition-minimized differential signaling) is both an electrical ...


6

The DONE pin in not used during JTAG programming and can be tied high: If JTAG is the only configuration mode, then PROGRAM_B, INIT_B, and DONE can be tied High to a 330Ω resistor. (p57) However, if Serial programming is used, then all the DONE pins should be tied together and the DriveDone should be disabled for all devices except the first: It is ...


6

The cat6a specifications are for 100m and 10Gb ethernet (so that's fine?) I think what you're trying to say with this is that if 10G Ethernet can transmit 100 m over Cat6A cable, then it should be possible to transmit 3.2 Gb/s over 50 m with the same cable. The difference between what it sounds like you want to do and how 10GbE does things is that the ...


6

In VHDL, if a port is declared "out", it can be assigned to, but it can't be used elsewhere inside the module. Specifically, the assignment on line 155 would be flagged as an error: OE <= RDA; Making the port "inout" makes this usage allowable. However, inout ports are "messy" for a number of reasons, and I try to avoid them wherever possible. Another ...


6

FPGA manufacturers don't use equivalent gate counts much any more, even in the hand-wavyest marketing materials. Like lines of code or megahertz of processor speed, it's a highly inaccurate metric for measuring the device capability, and in the FPGA markets the customers wised up enough to suppress its use. To estimate the size device you need, you'll need ...


6

the rising_edge() parameter is only really for clock signals. One option would be the following: clk_proc: process( clk, switch1, switch0 ) begin if switch1 = '1' then counter <= ( others => '0' ); elseif rising_edge( clk ) then if switch0 = '1' then counter <= counter + 1; end if; end if; end process;...


5

A few reasons why I believe using a microcontroller (MCU) would be easier for you: You have experience with MCUs. Learning the ins and outs of any new chip takes time. MCUs have inbuilt peripherals which you would have to implement yourself (or buy) on an FPGA. For example, most MCUs have an I2C port which will come in useful if you read from an I2C sensor. ...


5

Looking through your timing report, there is nothing that indicates a potential issue. Since you have a problem, this means that the scenarios that static timing analysis (STA) is checking are not covering the actual usage of your circuit. Without any serious setup of STA, some common assumptions are that all inputs are valid by the time the clock rises, ...


5

I think 3.2 Gbits over 50M is going to be nearly impossible over even the best single twisted pair. I think you would be better off going with coax if you can, single mode fiber even better. Look into the broadcast video market chipsets from TI/National. They have some nice SDI cable drivers and adaptive EQ that top off near 3Gbits. They will usually go ...


5

This is an SRAM-based FPGA. After cycling power, its configuration is lost! Normally a board using these FPGAs will have some non-volatile memory, and you load the configuration into that. The FPGA has some logic (configured by M0,M1,M2 the Configuration Mode pins) to boot itself from several common types of Flash memory or EEPROM. Some of them fit into the ...


5

I cross posted this question on the Xilinx Forum here: http://forums.xilinx.com/t5/Implementation/How-to-determine-what-part-of-the-design-consumes-the-most/td-p/393247 This answer is largely based on the comments there. Thanks to Deepika, Sikta and Gabor. First, enable 'Generate Detailed MAP Report' in the map process properties (-detail). Then, open the ...


5

Since answers should be written as answers and not comments, I'll summarize here: IEEE Std 1076-2008, section 15.7 - String literals A string literal has a value that is a sequence of character values corresponding to the graphic characters of the string literal apart from the quotation mark itself. If a quotation mark value is to be represented in the ...


4

You need to read the programming user guide. Shows on pg34. Micro drives PROGRAM_B, FPGA drives INIT_B.


4

Assuming the input is set to CMOS mode (you can choose between LVTTL and CMOS amongst others) then almost zero current is required (e.g. a few uA max) All you really need to be concerned about is the minimum logic high voltage, which will be stated in the datasheet (probably ~3V for 3.3V supply). The source/drive current for output pins can be set from 2mA ...


4

I believe you should be able to do this with 6 LUTs per cell. The basic approach is to divide the 8 inputs into two groups, 3 inputs in one group and 5 inputs in the other. You can count the ones in the first group with 2 LUTs, and count the ones in the second group with 3 LUTs, for a total of 5 intermediate result bits. One more LUT can combine those bits ...


4

I think it can fit in 3 LUTs but it won't be as elegant as David's solution. But reducing LUT is a goal, then this can work. Also, I have not worked with Spartan-6 FPGAs. I am basing this analysis on: http://www.xilinx.com/support/documentation/user_guides/ug384.pdf specifically figure 6 on page 13. Here it goes: LUT 0 is used as dual 5-input LUT. Its ...


4

FPGAs are more than just gates (LUTs, FFs, Block RAM, Multipliers, etc) and trying to work out how many there are is a fairly meaningless exercise. FPGA company marketing departments have, in the past, thrown numbers like equivalent gate counts equal to 1.4x the number of logic cells but I believe that they have stopped this practice. If you are trying to ...


4

The speed grade has to do mostly with specified transistor switching speed. You can review the definition of -MIN, -4 and -5 speed grades in appnote 312, page 125 onwards. This determines how quickly you can run internal clocked circuits. It will not influence the choice of your crystal oscillator, as you will use a PLL multiplier to generate the actual ...


4

The answer of the user36129 is pretty accurate, but in many cases, specially in the low cost FPGAs, the devices with the high performance are the one taken out of each batch after they prove to be faster than the "standard" defined on the specification of the device. Different companies have different ways of doing this, but I believe Xilinx tests ever ...


3

You say that you have found dividers that do "normal" division. Fixed-point division is normal division, except that the dividend must be scaled up (shifted left). Shift the dividend to the left 8 places (multiply by 256), then do a normal division. The fixed-point fractional result is equal to the integer result from the division, divided by 256. So, if you ...


3

\$5\mu s\$ is a lot slower than I would expect for a naive implementation, so you may have some other issues. Check the Floorplanner or FPGA Editor to see what the routed design actually looks like. You can try adding a "pad to pad" timing constraint if you have not done so already. But in general, asynchronous designs are discouraged for FPGAs. I am not ...


3

Solved it! The problem turned out to be that I was using the JTAG clock for the startup sequence, rather than CCLK. The choice of clock is specified inside the "Startup Options" inside ISE.


3

It turned out the culprit was the INIT_B pin. Although pulled high, as the first few FPGAs were programmed, the INIT_B pin was gradually pulled lower and lower because of an internal pull-down. After three FPGAs were programmed, the INIT_B pin was pulled low enough for the fourth FPGA to interpret INIT_B as a logic low, thereby preventing the fourth FGPA to ...


3

You need the script bitformat.pl to convert bit to bin. Select MAP is via a processor. You wish to look at XAPP502. In p. 4 is say you can use the .bit file if you skip the header. The bin file has no header information. Xilinx recommends .bin or .hex.


3

At least on Altera ALT_FP division component, the double precision 64bits division (52 bits mantissa) takes 10, 24 or 61 clock cycles (selectable). Single extended precision can vary. E.g. 43bits division where exponent is 11 bits, mantissa is 26 bits it allows to select such clock output latency options: 8, 18 or 35. Start ISE and check what You can have on ...


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