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7 votes
Accepted

Xilinx Spartan 3A programming connection : where are MISO and MOSI pins?

If you are expecting to be able to just use your programmer to load a configuration bitstream directly into the FPGA which only stores that in specialized SRAM, you are in for a surprise when it ...
DKNguyen's user avatar
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6 votes
Accepted

VHDL Delimiter Character

Since answers should be written as answers and not comments, I'll summarize here: IEEE Std 1076-2008, section 15.7 - String literals A string literal has a value that is a sequence of character ...
Dave Tweed's user avatar
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4 votes
Accepted

How to cross clock domains efficiently?

Assuming the data of interest changes on the falling edge of the 27Mhz clock and is sampled on the rising edge, the approach with minimal delay would be to have a divide-by-two clocked by the 27MHz ...
supercat's user avatar
  • 47k
4 votes

Xilinx Spartan 3A programming connection : where are MISO and MOSI pins?

For the XC3S50A-4VQG100C device you use the JTAG interface, not SPI. It has dedicated pins. JTAG is a somewhat similar interface to SPI but standardized for FPGAs, debug interfaces on many ...
Kevin White's user avatar
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3 votes

How can I program flash using Vitis?

So I finally figured it out. I positing it here for anyone who struggling with this. Vitis is not a great tool to do flash programming. Create a block design with Microblaze (guide on how to do this ...
Manny's user avatar
  • 79
2 votes
Accepted

How to probe into the internal signals and registers in FPGA without using JTAG?

One of the most useful ways to gain access to the internal register contents is to design it in!! First you have to decide the most convenient mechanism with which to access the FPGA. You could use a ...
Michael Karas's user avatar
2 votes

royalty free embedded processor

I have heard a lot of good stuff about vexriscv. In general, there is a lot of work around the riscv instruction set, in terms of compilers, soft processors, and all sorts of ASIC implementations.
alex.forencich's user avatar
2 votes

Why are All pins pull-up in SPARTAN 6?

There is a dedicated pin that defines whether there is a pull-up on all pins during configuration or not: HSWAPEN. The "Spartan-6 FPGA Configuration User Guide" UG380 contains all the ...
asdfex's user avatar
  • 3,104
1 vote
Accepted

Duplication of working PWM signal leads to unexpected behaviour

After one week of trying I figured out that the problem was caused by the JTAG programmer. I was using the JTAG programmer from Digilent with its Adept software. After switching to a Xilinx programmer ...
Ahmad's user avatar
  • 41
1 vote

royalty free embedded processor

I have been using the Instant Soc RISC-V in a couple of projects now. It really works great. It build an optimized RISC-V core and all around that based on your C++ code. It uses gcc and a compiler ...
Holminge's user avatar
  • 149
1 vote

royalty free embedded processor

The Hennessy & Patterson textbook now covers the RISCV architecture. Tons of academic papers on a wide range of RISCV implementations (including FPGA). Also there is a RISCV consortium ...
hotpaw2's user avatar
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1 vote

What are some good tips for handling PCB design for a spartan-6 LX9 microprocessor implementation?

The problem is that there are many, many techniques/rules. And the answer when to use then is (as usual) "it depends". Rules for decoupling, rules for high drive nets, rules for high speed nets. ...
Oldfart's user avatar
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1 vote

FDCE flip-flop primitive in Altera Quartus?

Newer versions of Quartus have wrappers for different basic flip-flop types. A list of all primitives can be found here: Primitive List for Quartus 15 Here is the DFFE component: ...
Paebbels's user avatar
  • 3,957
1 vote

How to count pressed keys on FPGA spartan board

You have an error in your code where you are attempting to make an assignment instead of a conditional evaluation: if Counter <= 15 then I'm assuming this should be: ...
Blair Fonville's user avatar
1 vote

How to count pressed keys on FPGA spartan board

Mechanical switches bounce when they are pressed. Your software needs to debounce the key press before considering it valid. This typically consists of delaying 30-70 ms after the initial key press is ...
Glenn W9IQ's user avatar
  • 5,594
1 vote

How to cross clock domains efficiently?

I couldn't exactly follow the entire scenario you described, but if the question just boils down to "what's a good way to pass a single clock cycle pulse into a different clock domain", considered ...
user2913869's user avatar
  • 1,101
1 vote

Unknown problem with I2C on Spartan 3-E {VERILOG}

The problem was with the hold time.Since the SDA line changed exactly on the falling edge of SCL, There was a hold time violation.I added a flip flop to produce a delay of around 600ns and the design ...
Ahmed Ali Abbasi's user avatar
1 vote

Verilog Error: System task finish is always executed

I was getting this problem too, the thing that was causing it for me was I was clicking the green arrow rather than right clicking "Simulate Behavioral Model" and selecting Run. The green arrow ...
Marshall Robin's user avatar
1 vote

Verilog Error: System task finish is always executed

So I installed ModelSim and that somehow convinced ISE to stop complaining about $finish. The weird thing is that I'm still not using a ModelSim simulator, it's ...
Liz P's user avatar
  • 21
1 vote

How do I reset my registers on Digital Clock Manager output?

I think your logic is correct, except you mean to implement an asynchronous reset .i.e the reset is independent of the clock. This doesn't reflect in the code above and can be fixed by adding the ...
dst's user avatar
  • 81
1 vote

HDMI (TMDS) output with Digilent Atlys - examples do not compile with ISE 14.7

Welcome to the world of Xilinx :) The problem is known, and I don't think they maintain this app very actively and if you search for the Answer Record mentioned in the error list, you will see that ...
FarhadA's user avatar
  • 1,379
1 vote
Accepted

Problem with implementation XAPP495

The XAPP495 does not have any form of EDID handling. However, as you are using the Digilent Atlys board, and are having one HDMI input and one HDMI output, then as long as you use the correct HDMI ...
Tom Carpenter's user avatar
1 vote

Benefit of using RAM, or some form of internal memory on a FPGA

The second part of your question (2D array vs. RAM) really comes down to the resources available on your FPGA. Usually storing something as large as an image or frame of video in logic elements isn't ...
Gipsy Danger's user avatar

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